1 /** @file 2 Provides services to access PCI Configuration Space. 3 4 These functions perform PCI configuration cycles using the default PCI configuration 5 access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, 6 or it may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some 7 alternate access method. Modules will typically use the PCI Library for its PCI configuration 8 accesses. However, if a module requires a mix of PCI access methods, the PCI CF8 Library or 9 PCI Express Library may be used in conjunction with the PCI Library. The functionality of 10 these three libraries is identical. The PCI CF8 Library and PCI Express Library simply use 11 explicit access methods. 12 13 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR> 14 This program and the accompanying materials 15 are licensed and made available under the terms and conditions of the BSD License 16 which accompanies this distribution. The full text of the license may be found at 17 http://opensource.org/licenses/bsd-license.php 18 19 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 20 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 21 22 **/ 23 24 #ifndef __PCI_LIB_H__ 25 #define __PCI_LIB_H__ 26 27 /** 28 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an 29 address that can be passed to the PCI Library functions. 30 31 @param Bus PCI Bus number. Range 0..255. 32 @param Device PCI Device number. Range 0..31. 33 @param Function PCI Function number. Range 0..7. 34 @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 35 for PCI Express. 36 37 @return The encoded PCI address. 38 39 **/ 40 #define PCI_LIB_ADDRESS(Bus,Device,Function,Register) \ 41 (((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20)) 42 43 /** 44 Registers a PCI device so PCI configuration registers may be accessed after 45 SetVirtualAddressMap(). 46 47 Registers the PCI device specified by Address so all the PCI configuration registers 48 associated with that PCI device may be accessed after SetVirtualAddressMap() is called. 49 50 If Address > 0x0FFFFFFF, then ASSERT(). 51 52 @param Address Address that encodes the PCI Bus, Device, Function and 53 Register. 54 55 @retval RETURN_SUCCESS The PCI device was registered for runtime access. 56 @retval RETURN_UNSUPPORTED An attempt was made to call this function 57 after ExitBootServices(). 58 @retval RETURN_UNSUPPORTED The resources required to access the PCI device 59 at runtime could not be mapped. 60 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to 61 complete the registration. 62 63 **/ 64 RETURN_STATUS 65 EFIAPI 66 PciRegisterForRuntimeAccess ( 67 IN UINTN Address 68 ); 69 70 /** 71 Reads an 8-bit PCI configuration register. 72 73 Reads and returns the 8-bit PCI configuration register specified by Address. 74 This function must guarantee that all PCI read and write operations are 75 serialized. 76 77 If Address > 0x0FFFFFFF, then ASSERT(). 78 79 @param Address Address that encodes the PCI Bus, Device, Function and 80 Register. 81 82 @return The read value from the PCI configuration register. 83 84 **/ 85 UINT8 86 EFIAPI 87 PciRead8 ( 88 IN UINTN Address 89 ); 90 91 /** 92 Writes an 8-bit PCI configuration register. 93 94 Writes the 8-bit PCI configuration register specified by Address with the 95 value specified by Value. Value is returned. This function must guarantee 96 that all PCI read and write operations are serialized. 97 98 If Address > 0x0FFFFFFF, then ASSERT(). 99 100 @param Address Address that encodes the PCI Bus, Device, Function and 101 Register. 102 @param Value The value to write. 103 104 @return The value written to the PCI configuration register. 105 106 **/ 107 UINT8 108 EFIAPI 109 PciWrite8 ( 110 IN UINTN Address, 111 IN UINT8 Value 112 ); 113 114 /** 115 Performs a bitwise OR of an 8-bit PCI configuration register with 116 an 8-bit value. 117 118 Reads the 8-bit PCI configuration register specified by Address, performs a 119 bitwise OR between the read result and the value specified by 120 OrData, and writes the result to the 8-bit PCI configuration register 121 specified by Address. The value written to the PCI configuration register is 122 returned. This function must guarantee that all PCI read and write operations 123 are serialized. 124 125 If Address > 0x0FFFFFFF, then ASSERT(). 126 127 @param Address Address that encodes the PCI Bus, Device, Function and 128 Register. 129 @param OrData The value to OR with the PCI configuration register. 130 131 @return The value written back to the PCI configuration register. 132 133 **/ 134 UINT8 135 EFIAPI 136 PciOr8 ( 137 IN UINTN Address, 138 IN UINT8 OrData 139 ); 140 141 /** 142 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit 143 value. 144 145 Reads the 8-bit PCI configuration register specified by Address, performs a 146 bitwise AND between the read result and the value specified by AndData, and 147 writes the result to the 8-bit PCI configuration register specified by 148 Address. The value written to the PCI configuration register is returned. 149 This function must guarantee that all PCI read and write operations are 150 serialized. 151 152 If Address > 0x0FFFFFFF, then ASSERT(). 153 154 @param Address Address that encodes the PCI Bus, Device, Function and 155 Register. 156 @param AndData The value to AND with the PCI configuration register. 157 158 @return The value written back to the PCI configuration register. 159 160 **/ 161 UINT8 162 EFIAPI 163 PciAnd8 ( 164 IN UINTN Address, 165 IN UINT8 AndData 166 ); 167 168 /** 169 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit 170 value, followed by a bitwise OR with another 8-bit value. 171 172 Reads the 8-bit PCI configuration register specified by Address, performs a 173 bitwise AND between the read result and the value specified by AndData, 174 performs a bitwise OR between the result of the AND operation and 175 the value specified by OrData, and writes the result to the 8-bit PCI 176 configuration register specified by Address. The value written to the PCI 177 configuration register is returned. This function must guarantee that all PCI 178 read and write operations are serialized. 179 180 If Address > 0x0FFFFFFF, then ASSERT(). 181 182 @param Address Address that encodes the PCI Bus, Device, Function and 183 Register. 184 @param AndData The value to AND with the PCI configuration register. 185 @param OrData The value to OR with the result of the AND operation. 186 187 @return The value written back to the PCI configuration register. 188 189 **/ 190 UINT8 191 EFIAPI 192 PciAndThenOr8 ( 193 IN UINTN Address, 194 IN UINT8 AndData, 195 IN UINT8 OrData 196 ); 197 198 /** 199 Reads a bit field of a PCI configuration register. 200 201 Reads the bit field in an 8-bit PCI configuration register. The bit field is 202 specified by the StartBit and the EndBit. The value of the bit field is 203 returned. 204 205 If Address > 0x0FFFFFFF, then ASSERT(). 206 If StartBit is greater than 7, then ASSERT(). 207 If EndBit is greater than 7, then ASSERT(). 208 If EndBit is less than StartBit, then ASSERT(). 209 210 @param Address PCI configuration register to read. 211 @param StartBit The ordinal of the least significant bit in the bit field. 212 Range 0..7. 213 @param EndBit The ordinal of the most significant bit in the bit field. 214 Range 0..7. 215 216 @return The value of the bit field read from the PCI configuration register. 217 218 **/ 219 UINT8 220 EFIAPI 221 PciBitFieldRead8 ( 222 IN UINTN Address, 223 IN UINTN StartBit, 224 IN UINTN EndBit 225 ); 226 227 /** 228 Writes a bit field to a PCI configuration register. 229 230 Writes Value to the bit field of the PCI configuration register. The bit 231 field is specified by the StartBit and the EndBit. All other bits in the 232 destination PCI configuration register are preserved. The new value of the 233 8-bit register is returned. 234 235 If Address > 0x0FFFFFFF, then ASSERT(). 236 If StartBit is greater than 7, then ASSERT(). 237 If EndBit is greater than 7, then ASSERT(). 238 If EndBit is less than StartBit, then ASSERT(). 239 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 240 241 @param Address PCI configuration register to write. 242 @param StartBit The ordinal of the least significant bit in the bit field. 243 Range 0..7. 244 @param EndBit The ordinal of the most significant bit in the bit field. 245 Range 0..7. 246 @param Value New value of the bit field. 247 248 @return The value written back to the PCI configuration register. 249 250 **/ 251 UINT8 252 EFIAPI 253 PciBitFieldWrite8 ( 254 IN UINTN Address, 255 IN UINTN StartBit, 256 IN UINTN EndBit, 257 IN UINT8 Value 258 ); 259 260 /** 261 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and 262 writes the result back to the bit field in the 8-bit port. 263 264 Reads the 8-bit PCI configuration register specified by Address, performs a 265 bitwise OR between the read result and the value specified by 266 OrData, and writes the result to the 8-bit PCI configuration register 267 specified by Address. The value written to the PCI configuration register is 268 returned. This function must guarantee that all PCI read and write operations 269 are serialized. Extra left bits in OrData are stripped. 270 271 If Address > 0x0FFFFFFF, then ASSERT(). 272 If StartBit is greater than 7, then ASSERT(). 273 If EndBit is greater than 7, then ASSERT(). 274 If EndBit is less than StartBit, then ASSERT(). 275 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 276 277 @param Address PCI configuration register to write. 278 @param StartBit The ordinal of the least significant bit in the bit field. 279 Range 0..7. 280 @param EndBit The ordinal of the most significant bit in the bit field. 281 Range 0..7. 282 @param OrData The value to OR with the PCI configuration register. 283 284 @return The value written back to the PCI configuration register. 285 286 **/ 287 UINT8 288 EFIAPI 289 PciBitFieldOr8 ( 290 IN UINTN Address, 291 IN UINTN StartBit, 292 IN UINTN EndBit, 293 IN UINT8 OrData 294 ); 295 296 /** 297 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise 298 AND, and writes the result back to the bit field in the 8-bit register. 299 300 Reads the 8-bit PCI configuration register specified by Address, performs a 301 bitwise AND between the read result and the value specified by AndData, and 302 writes the result to the 8-bit PCI configuration register specified by 303 Address. The value written to the PCI configuration register is returned. 304 This function must guarantee that all PCI read and write operations are 305 serialized. Extra left bits in AndData are stripped. 306 307 If Address > 0x0FFFFFFF, then ASSERT(). 308 If StartBit is greater than 7, then ASSERT(). 309 If EndBit is greater than 7, then ASSERT(). 310 If EndBit is less than StartBit, then ASSERT(). 311 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 312 313 @param Address PCI configuration register to write. 314 @param StartBit The ordinal of the least significant bit in the bit field. 315 Range 0..7. 316 @param EndBit The ordinal of the most significant bit in the bit field. 317 Range 0..7. 318 @param AndData The value to AND with the PCI configuration register. 319 320 @return The value written back to the PCI configuration register. 321 322 **/ 323 UINT8 324 EFIAPI 325 PciBitFieldAnd8 ( 326 IN UINTN Address, 327 IN UINTN StartBit, 328 IN UINTN EndBit, 329 IN UINT8 AndData 330 ); 331 332 /** 333 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a 334 bitwise OR, and writes the result back to the bit field in the 335 8-bit port. 336 337 Reads the 8-bit PCI configuration register specified by Address, performs a 338 bitwise AND followed by a bitwise OR between the read result and 339 the value specified by AndData, and writes the result to the 8-bit PCI 340 configuration register specified by Address. The value written to the PCI 341 configuration register is returned. This function must guarantee that all PCI 342 read and write operations are serialized. Extra left bits in both AndData and 343 OrData are stripped. 344 345 If Address > 0x0FFFFFFF, then ASSERT(). 346 If StartBit is greater than 7, then ASSERT(). 347 If EndBit is greater than 7, then ASSERT(). 348 If EndBit is less than StartBit, then ASSERT(). 349 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 350 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 351 352 @param Address PCI configuration register to write. 353 @param StartBit The ordinal of the least significant bit in the bit field. 354 Range 0..7. 355 @param EndBit The ordinal of the most significant bit in the bit field. 356 Range 0..7. 357 @param AndData The value to AND with the PCI configuration register. 358 @param OrData The value to OR with the result of the AND operation. 359 360 @return The value written back to the PCI configuration register. 361 362 **/ 363 UINT8 364 EFIAPI 365 PciBitFieldAndThenOr8 ( 366 IN UINTN Address, 367 IN UINTN StartBit, 368 IN UINTN EndBit, 369 IN UINT8 AndData, 370 IN UINT8 OrData 371 ); 372 373 /** 374 Reads a 16-bit PCI configuration register. 375 376 Reads and returns the 16-bit PCI configuration register specified by Address. 377 This function must guarantee that all PCI read and write operations are 378 serialized. 379 380 If Address > 0x0FFFFFFF, then ASSERT(). 381 If Address is not aligned on a 16-bit boundary, then ASSERT(). 382 383 @param Address Address that encodes the PCI Bus, Device, Function and 384 Register. 385 386 @return The read value from the PCI configuration register. 387 388 **/ 389 UINT16 390 EFIAPI 391 PciRead16 ( 392 IN UINTN Address 393 ); 394 395 /** 396 Writes a 16-bit PCI configuration register. 397 398 Writes the 16-bit PCI configuration register specified by Address with the 399 value specified by Value. Value is returned. This function must guarantee 400 that all PCI read and write operations are serialized. 401 402 If Address > 0x0FFFFFFF, then ASSERT(). 403 If Address is not aligned on a 16-bit boundary, then ASSERT(). 404 405 @param Address Address that encodes the PCI Bus, Device, Function and 406 Register. 407 @param Value The value to write. 408 409 @return The value written to the PCI configuration register. 410 411 **/ 412 UINT16 413 EFIAPI 414 PciWrite16 ( 415 IN UINTN Address, 416 IN UINT16 Value 417 ); 418 419 /** 420 Performs a bitwise OR of a 16-bit PCI configuration register with 421 a 16-bit value. 422 423 Reads the 16-bit PCI configuration register specified by Address, performs a 424 bitwise OR between the read result and the value specified by 425 OrData, and writes the result to the 16-bit PCI configuration register 426 specified by Address. The value written to the PCI configuration register is 427 returned. This function must guarantee that all PCI read and write operations 428 are serialized. 429 430 If Address > 0x0FFFFFFF, then ASSERT(). 431 If Address is not aligned on a 16-bit boundary, then ASSERT(). 432 433 @param Address Address that encodes the PCI Bus, Device, Function and 434 Register. 435 @param OrData The value to OR with the PCI configuration register. 436 437 @return The value written back to the PCI configuration register. 438 439 **/ 440 UINT16 441 EFIAPI 442 PciOr16 ( 443 IN UINTN Address, 444 IN UINT16 OrData 445 ); 446 447 /** 448 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit 449 value. 450 451 Reads the 16-bit PCI configuration register specified by Address, performs a 452 bitwise AND between the read result and the value specified by AndData, and 453 writes the result to the 16-bit PCI configuration register specified by 454 Address. The value written to the PCI configuration register is returned. 455 This function must guarantee that all PCI read and write operations are 456 serialized. 457 458 If Address > 0x0FFFFFFF, then ASSERT(). 459 If Address is not aligned on a 16-bit boundary, then ASSERT(). 460 461 @param Address Address that encodes the PCI Bus, Device, Function and 462 Register. 463 @param AndData The value to AND with the PCI configuration register. 464 465 @return The value written back to the PCI configuration register. 466 467 **/ 468 UINT16 469 EFIAPI 470 PciAnd16 ( 471 IN UINTN Address, 472 IN UINT16 AndData 473 ); 474 475 /** 476 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit 477 value, followed a bitwise OR with another 16-bit value. 478 479 Reads the 16-bit PCI configuration register specified by Address, performs a 480 bitwise AND between the read result and the value specified by AndData, 481 performs a bitwise OR between the result of the AND operation and 482 the value specified by OrData, and writes the result to the 16-bit PCI 483 configuration register specified by Address. The value written to the PCI 484 configuration register is returned. This function must guarantee that all PCI 485 read and write operations are serialized. 486 487 If Address > 0x0FFFFFFF, then ASSERT(). 488 If Address is not aligned on a 16-bit boundary, then ASSERT(). 489 490 @param Address Address that encodes the PCI Bus, Device, Function and 491 Register. 492 @param AndData The value to AND with the PCI configuration register. 493 @param OrData The value to OR with the result of the AND operation. 494 495 @return The value written back to the PCI configuration register. 496 497 **/ 498 UINT16 499 EFIAPI 500 PciAndThenOr16 ( 501 IN UINTN Address, 502 IN UINT16 AndData, 503 IN UINT16 OrData 504 ); 505 506 /** 507 Reads a bit field of a PCI configuration register. 508 509 Reads the bit field in a 16-bit PCI configuration register. The bit field is 510 specified by the StartBit and the EndBit. The value of the bit field is 511 returned. 512 513 If Address > 0x0FFFFFFF, then ASSERT(). 514 If Address is not aligned on a 16-bit boundary, then ASSERT(). 515 If StartBit is greater than 15, then ASSERT(). 516 If EndBit is greater than 15, then ASSERT(). 517 If EndBit is less than StartBit, then ASSERT(). 518 519 @param Address PCI configuration register to read. 520 @param StartBit The ordinal of the least significant bit in the bit field. 521 Range 0..15. 522 @param EndBit The ordinal of the most significant bit in the bit field. 523 Range 0..15. 524 525 @return The value of the bit field read from the PCI configuration register. 526 527 **/ 528 UINT16 529 EFIAPI 530 PciBitFieldRead16 ( 531 IN UINTN Address, 532 IN UINTN StartBit, 533 IN UINTN EndBit 534 ); 535 536 /** 537 Writes a bit field to a PCI configuration register. 538 539 Writes Value to the bit field of the PCI configuration register. The bit 540 field is specified by the StartBit and the EndBit. All other bits in the 541 destination PCI configuration register are preserved. The new value of the 542 16-bit register is returned. 543 544 If Address > 0x0FFFFFFF, then ASSERT(). 545 If Address is not aligned on a 16-bit boundary, then ASSERT(). 546 If StartBit is greater than 15, then ASSERT(). 547 If EndBit is greater than 15, then ASSERT(). 548 If EndBit is less than StartBit, then ASSERT(). 549 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 550 551 @param Address PCI configuration register to write. 552 @param StartBit The ordinal of the least significant bit in the bit field. 553 Range 0..15. 554 @param EndBit The ordinal of the most significant bit in the bit field. 555 Range 0..15. 556 @param Value New value of the bit field. 557 558 @return The value written back to the PCI configuration register. 559 560 **/ 561 UINT16 562 EFIAPI 563 PciBitFieldWrite16 ( 564 IN UINTN Address, 565 IN UINTN StartBit, 566 IN UINTN EndBit, 567 IN UINT16 Value 568 ); 569 570 /** 571 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and 572 writes the result back to the bit field in the 16-bit port. 573 574 Reads the 16-bit PCI configuration register specified by Address, performs a 575 bitwise OR between the read result and the value specified by 576 OrData, and writes the result to the 16-bit PCI configuration register 577 specified by Address. The value written to the PCI configuration register is 578 returned. This function must guarantee that all PCI read and write operations 579 are serialized. Extra left bits in OrData are stripped. 580 581 If Address > 0x0FFFFFFF, then ASSERT(). 582 If Address is not aligned on a 16-bit boundary, then ASSERT(). 583 If StartBit is greater than 15, then ASSERT(). 584 If EndBit is greater than 15, then ASSERT(). 585 If EndBit is less than StartBit, then ASSERT(). 586 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 587 588 @param Address PCI configuration register to write. 589 @param StartBit The ordinal of the least significant bit in the bit field. 590 Range 0..15. 591 @param EndBit The ordinal of the most significant bit in the bit field. 592 Range 0..15. 593 @param OrData The value to OR with the PCI configuration register. 594 595 @return The value written back to the PCI configuration register. 596 597 **/ 598 UINT16 599 EFIAPI 600 PciBitFieldOr16 ( 601 IN UINTN Address, 602 IN UINTN StartBit, 603 IN UINTN EndBit, 604 IN UINT16 OrData 605 ); 606 607 /** 608 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise 609 AND, and writes the result back to the bit field in the 16-bit register. 610 611 Reads the 16-bit PCI configuration register specified by Address, performs a 612 bitwise AND between the read result and the value specified by AndData, and 613 writes the result to the 16-bit PCI configuration register specified by 614 Address. The value written to the PCI configuration register is returned. 615 This function must guarantee that all PCI read and write operations are 616 serialized. Extra left bits in AndData are stripped. 617 618 If Address > 0x0FFFFFFF, then ASSERT(). 619 If Address is not aligned on a 16-bit boundary, then ASSERT(). 620 If StartBit is greater than 15, then ASSERT(). 621 If EndBit is greater than 15, then ASSERT(). 622 If EndBit is less than StartBit, then ASSERT(). 623 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 624 625 @param Address PCI configuration register to write. 626 @param StartBit The ordinal of the least significant bit in the bit field. 627 Range 0..15. 628 @param EndBit The ordinal of the most significant bit in the bit field. 629 Range 0..15. 630 @param AndData The value to AND with the PCI configuration register. 631 632 @return The value written back to the PCI configuration register. 633 634 **/ 635 UINT16 636 EFIAPI 637 PciBitFieldAnd16 ( 638 IN UINTN Address, 639 IN UINTN StartBit, 640 IN UINTN EndBit, 641 IN UINT16 AndData 642 ); 643 644 /** 645 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a 646 bitwise OR, and writes the result back to the bit field in the 647 16-bit port. 648 649 Reads the 16-bit PCI configuration register specified by Address, performs a 650 bitwise AND followed by a bitwise OR between the read result and 651 the value specified by AndData, and writes the result to the 16-bit PCI 652 configuration register specified by Address. The value written to the PCI 653 configuration register is returned. This function must guarantee that all PCI 654 read and write operations are serialized. Extra left bits in both AndData and 655 OrData are stripped. 656 657 If Address > 0x0FFFFFFF, then ASSERT(). 658 If Address is not aligned on a 16-bit boundary, then ASSERT(). 659 If StartBit is greater than 15, then ASSERT(). 660 If EndBit is greater than 15, then ASSERT(). 661 If EndBit is less than StartBit, then ASSERT(). 662 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 663 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 664 665 @param Address PCI configuration register to write. 666 @param StartBit The ordinal of the least significant bit in the bit field. 667 Range 0..15. 668 @param EndBit The ordinal of the most significant bit in the bit field. 669 Range 0..15. 670 @param AndData The value to AND with the PCI configuration register. 671 @param OrData The value to OR with the result of the AND operation. 672 673 @return The value written back to the PCI configuration register. 674 675 **/ 676 UINT16 677 EFIAPI 678 PciBitFieldAndThenOr16 ( 679 IN UINTN Address, 680 IN UINTN StartBit, 681 IN UINTN EndBit, 682 IN UINT16 AndData, 683 IN UINT16 OrData 684 ); 685 686 /** 687 Reads a 32-bit PCI configuration register. 688 689 Reads and returns the 32-bit PCI configuration register specified by Address. 690 This function must guarantee that all PCI read and write operations are 691 serialized. 692 693 If Address > 0x0FFFFFFF, then ASSERT(). 694 If Address is not aligned on a 32-bit boundary, then ASSERT(). 695 696 @param Address Address that encodes the PCI Bus, Device, Function and 697 Register. 698 699 @return The read value from the PCI configuration register. 700 701 **/ 702 UINT32 703 EFIAPI 704 PciRead32 ( 705 IN UINTN Address 706 ); 707 708 /** 709 Writes a 32-bit PCI configuration register. 710 711 Writes the 32-bit PCI configuration register specified by Address with the 712 value specified by Value. Value is returned. This function must guarantee 713 that all PCI read and write operations are serialized. 714 715 If Address > 0x0FFFFFFF, then ASSERT(). 716 If Address is not aligned on a 32-bit boundary, then ASSERT(). 717 718 @param Address Address that encodes the PCI Bus, Device, Function and 719 Register. 720 @param Value The value to write. 721 722 @return The value written to the PCI configuration register. 723 724 **/ 725 UINT32 726 EFIAPI 727 PciWrite32 ( 728 IN UINTN Address, 729 IN UINT32 Value 730 ); 731 732 /** 733 Performs a bitwise OR of a 32-bit PCI configuration register with 734 a 32-bit value. 735 736 Reads the 32-bit PCI configuration register specified by Address, performs a 737 bitwise OR between the read result and the value specified by 738 OrData, and writes the result to the 32-bit PCI configuration register 739 specified by Address. The value written to the PCI configuration register is 740 returned. This function must guarantee that all PCI read and write operations 741 are serialized. 742 743 If Address > 0x0FFFFFFF, then ASSERT(). 744 If Address is not aligned on a 32-bit boundary, then ASSERT(). 745 746 @param Address Address that encodes the PCI Bus, Device, Function and 747 Register. 748 @param OrData The value to OR with the PCI configuration register. 749 750 @return The value written back to the PCI configuration register. 751 752 **/ 753 UINT32 754 EFIAPI 755 PciOr32 ( 756 IN UINTN Address, 757 IN UINT32 OrData 758 ); 759 760 /** 761 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit 762 value. 763 764 Reads the 32-bit PCI configuration register specified by Address, performs a 765 bitwise AND between the read result and the value specified by AndData, and 766 writes the result to the 32-bit PCI configuration register specified by 767 Address. The value written to the PCI configuration register is returned. 768 This function must guarantee that all PCI read and write operations are 769 serialized. 770 771 If Address > 0x0FFFFFFF, then ASSERT(). 772 If Address is not aligned on a 32-bit boundary, then ASSERT(). 773 774 @param Address Address that encodes the PCI Bus, Device, Function and 775 Register. 776 @param AndData The value to AND with the PCI configuration register. 777 778 @return The value written back to the PCI configuration register. 779 780 **/ 781 UINT32 782 EFIAPI 783 PciAnd32 ( 784 IN UINTN Address, 785 IN UINT32 AndData 786 ); 787 788 /** 789 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit 790 value, followed a bitwise OR with another 32-bit value. 791 792 Reads the 32-bit PCI configuration register specified by Address, performs a 793 bitwise AND between the read result and the value specified by AndData, 794 performs a bitwise OR between the result of the AND operation and 795 the value specified by OrData, and writes the result to the 32-bit PCI 796 configuration register specified by Address. The value written to the PCI 797 configuration register is returned. This function must guarantee that all PCI 798 read and write operations are serialized. 799 800 If Address > 0x0FFFFFFF, then ASSERT(). 801 If Address is not aligned on a 32-bit boundary, then ASSERT(). 802 803 @param Address Address that encodes the PCI Bus, Device, Function and 804 Register. 805 @param AndData The value to AND with the PCI configuration register. 806 @param OrData The value to OR with the result of the AND operation. 807 808 @return The value written back to the PCI configuration register. 809 810 **/ 811 UINT32 812 EFIAPI 813 PciAndThenOr32 ( 814 IN UINTN Address, 815 IN UINT32 AndData, 816 IN UINT32 OrData 817 ); 818 819 /** 820 Reads a bit field of a PCI configuration register. 821 822 Reads the bit field in a 32-bit PCI configuration register. The bit field is 823 specified by the StartBit and the EndBit. The value of the bit field is 824 returned. 825 826 If Address > 0x0FFFFFFF, then ASSERT(). 827 If Address is not aligned on a 32-bit boundary, then ASSERT(). 828 If StartBit is greater than 31, then ASSERT(). 829 If EndBit is greater than 31, then ASSERT(). 830 If EndBit is less than StartBit, then ASSERT(). 831 832 @param Address PCI configuration register to read. 833 @param StartBit The ordinal of the least significant bit in the bit field. 834 Range 0..31. 835 @param EndBit The ordinal of the most significant bit in the bit field. 836 Range 0..31. 837 838 @return The value of the bit field read from the PCI configuration register. 839 840 **/ 841 UINT32 842 EFIAPI 843 PciBitFieldRead32 ( 844 IN UINTN Address, 845 IN UINTN StartBit, 846 IN UINTN EndBit 847 ); 848 849 /** 850 Writes a bit field to a PCI configuration register. 851 852 Writes Value to the bit field of the PCI configuration register. The bit 853 field is specified by the StartBit and the EndBit. All other bits in the 854 destination PCI configuration register are preserved. The new value of the 855 32-bit register is returned. 856 857 If Address > 0x0FFFFFFF, then ASSERT(). 858 If Address is not aligned on a 32-bit boundary, then ASSERT(). 859 If StartBit is greater than 31, then ASSERT(). 860 If EndBit is greater than 31, then ASSERT(). 861 If EndBit is less than StartBit, then ASSERT(). 862 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 863 864 @param Address PCI configuration register to write. 865 @param StartBit The ordinal of the least significant bit in the bit field. 866 Range 0..31. 867 @param EndBit The ordinal of the most significant bit in the bit field. 868 Range 0..31. 869 @param Value New value of the bit field. 870 871 @return The value written back to the PCI configuration register. 872 873 **/ 874 UINT32 875 EFIAPI 876 PciBitFieldWrite32 ( 877 IN UINTN Address, 878 IN UINTN StartBit, 879 IN UINTN EndBit, 880 IN UINT32 Value 881 ); 882 883 /** 884 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and 885 writes the result back to the bit field in the 32-bit port. 886 887 Reads the 32-bit PCI configuration register specified by Address, performs a 888 bitwise OR between the read result and the value specified by 889 OrData, and writes the result to the 32-bit PCI configuration register 890 specified by Address. The value written to the PCI configuration register is 891 returned. This function must guarantee that all PCI read and write operations 892 are serialized. Extra left bits in OrData are stripped. 893 894 If Address > 0x0FFFFFFF, then ASSERT(). 895 If Address is not aligned on a 32-bit boundary, then ASSERT(). 896 If StartBit is greater than 31, then ASSERT(). 897 If EndBit is greater than 31, then ASSERT(). 898 If EndBit is less than StartBit, then ASSERT(). 899 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 900 901 @param Address PCI configuration register to write. 902 @param StartBit The ordinal of the least significant bit in the bit field. 903 Range 0..31. 904 @param EndBit The ordinal of the most significant bit in the bit field. 905 Range 0..31. 906 @param OrData The value to OR with the PCI configuration register. 907 908 @return The value written back to the PCI configuration register. 909 910 **/ 911 UINT32 912 EFIAPI 913 PciBitFieldOr32 ( 914 IN UINTN Address, 915 IN UINTN StartBit, 916 IN UINTN EndBit, 917 IN UINT32 OrData 918 ); 919 920 /** 921 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise 922 AND, and writes the result back to the bit field in the 32-bit register. 923 924 Reads the 32-bit PCI configuration register specified by Address, performs a 925 bitwise AND between the read result and the value specified by AndData, and 926 writes the result to the 32-bit PCI configuration register specified by 927 Address. The value written to the PCI configuration register is returned. 928 This function must guarantee that all PCI read and write operations are 929 serialized. Extra left bits in AndData are stripped. 930 931 If Address > 0x0FFFFFFF, then ASSERT(). 932 If Address is not aligned on a 32-bit boundary, then ASSERT(). 933 If StartBit is greater than 31, then ASSERT(). 934 If EndBit is greater than 31, then ASSERT(). 935 If EndBit is less than StartBit, then ASSERT(). 936 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 937 938 @param Address PCI configuration register to write. 939 @param StartBit The ordinal of the least significant bit in the bit field. 940 Range 0..31. 941 @param EndBit The ordinal of the most significant bit in the bit field. 942 Range 0..31. 943 @param AndData The value to AND with the PCI configuration register. 944 945 @return The value written back to the PCI configuration register. 946 947 **/ 948 UINT32 949 EFIAPI 950 PciBitFieldAnd32 ( 951 IN UINTN Address, 952 IN UINTN StartBit, 953 IN UINTN EndBit, 954 IN UINT32 AndData 955 ); 956 957 /** 958 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a 959 bitwise OR, and writes the result back to the bit field in the 960 32-bit port. 961 962 Reads the 32-bit PCI configuration register specified by Address, performs a 963 bitwise AND followed by a bitwise OR between the read result and 964 the value specified by AndData, and writes the result to the 32-bit PCI 965 configuration register specified by Address. The value written to the PCI 966 configuration register is returned. This function must guarantee that all PCI 967 read and write operations are serialized. Extra left bits in both AndData and 968 OrData are stripped. 969 970 If Address > 0x0FFFFFFF, then ASSERT(). 971 If Address is not aligned on a 32-bit boundary, then ASSERT(). 972 If StartBit is greater than 31, then ASSERT(). 973 If EndBit is greater than 31, then ASSERT(). 974 If EndBit is less than StartBit, then ASSERT(). 975 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 976 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). 977 978 @param Address PCI configuration register to write. 979 @param StartBit The ordinal of the least significant bit in the bit field. 980 Range 0..31. 981 @param EndBit The ordinal of the most significant bit in the bit field. 982 Range 0..31. 983 @param AndData The value to AND with the PCI configuration register. 984 @param OrData The value to OR with the result of the AND operation. 985 986 @return The value written back to the PCI configuration register. 987 988 **/ 989 UINT32 990 EFIAPI 991 PciBitFieldAndThenOr32 ( 992 IN UINTN Address, 993 IN UINTN StartBit, 994 IN UINTN EndBit, 995 IN UINT32 AndData, 996 IN UINT32 OrData 997 ); 998 999 /** 1000 Reads a range of PCI configuration registers into a caller supplied buffer. 1001 1002 Reads the range of PCI configuration registers specified by StartAddress and 1003 Size into the buffer specified by Buffer. This function only allows the PCI 1004 configuration registers from a single PCI function to be read. Size is 1005 returned. When possible 32-bit PCI configuration read cycles are used to read 1006 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit 1007 and 16-bit PCI configuration read cycles may be used at the beginning and the 1008 end of the range. 1009 1010 If StartAddress > 0x0FFFFFFF, then ASSERT(). 1011 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). 1012 If Size > 0 and Buffer is NULL, then ASSERT(). 1013 1014 @param StartAddress Starting address that encodes the PCI Bus, Device, 1015 Function and Register. 1016 @param Size Size in bytes of the transfer. 1017 @param Buffer Pointer to a buffer receiving the data read. 1018 1019 @return Size 1020 1021 **/ 1022 UINTN 1023 EFIAPI 1024 PciReadBuffer ( 1025 IN UINTN StartAddress, 1026 IN UINTN Size, 1027 OUT VOID *Buffer 1028 ); 1029 1030 /** 1031 Copies the data in a caller supplied buffer to a specified range of PCI 1032 configuration space. 1033 1034 Writes the range of PCI configuration registers specified by StartAddress and 1035 Size from the buffer specified by Buffer. This function only allows the PCI 1036 configuration registers from a single PCI function to be written. Size is 1037 returned. When possible 32-bit PCI configuration write cycles are used to 1038 write from StartAdress to StartAddress + Size. Due to alignment restrictions, 1039 8-bit and 16-bit PCI configuration write cycles may be used at the beginning 1040 and the end of the range. 1041 1042 If StartAddress > 0x0FFFFFFF, then ASSERT(). 1043 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). 1044 If Size > 0 and Buffer is NULL, then ASSERT(). 1045 1046 @param StartAddress Starting address that encodes the PCI Bus, Device, 1047 Function and Register. 1048 @param Size Size in bytes of the transfer. 1049 @param Buffer Pointer to a buffer containing the data to write. 1050 1051 @return Size written to StartAddress. 1052 1053 **/ 1054 UINTN 1055 EFIAPI 1056 PciWriteBuffer ( 1057 IN UINTN StartAddress, 1058 IN UINTN Size, 1059 IN VOID *Buffer 1060 ); 1061 1062 #endif 1063