1;------------------------------------------------------------------------------ ; 2; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 3; This program and the accompanying materials 4; are licensed and made available under the terms and conditions of the BSD License 5; which accompanies this distribution. The full text of the license may be found at 6; http://opensource.org/licenses/bsd-license.php. 7; 8; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 9; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 10; 11; Module Name: 12; 13; SmiException.nasm 14; 15; Abstract: 16; 17; Exception handlers used in SM mode 18; 19;------------------------------------------------------------------------------- 20 21global ASM_PFX(gcStmPsd) 22 23extern ASM_PFX(SmmStmExceptionHandler) 24extern ASM_PFX(SmmStmSetup) 25extern ASM_PFX(SmmStmTeardown) 26extern ASM_PFX(gStmXdSupported) 27extern ASM_PFX(gStmSmiHandlerIdtr) 28 29%define MSR_IA32_MISC_ENABLE 0x1A0 30%define MSR_EFER 0xc0000080 31%define MSR_EFER_XD 0x800 32 33CODE_SEL equ 0x38 34DATA_SEL equ 0x20 35TR_SEL equ 0x40 36 37 SECTION .data 38 39; 40; This structure serves as a template for all processors. 41; 42ASM_PFX(gcStmPsd): 43 DB 'TXTPSSIG' 44 DW PSD_SIZE 45 DW 1 ; Version 46 DD 0 ; LocalApicId 47 DB 0x0F ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr 48 DB 0 ; BIOS to STM 49 DB 0 ; STM to BIOS 50 DB 0 51 DW CODE_SEL 52 DW DATA_SEL 53 DW DATA_SEL 54 DW DATA_SEL 55 DW TR_SEL 56 DW 0 57 DQ 0 ; SmmCr3 58 DQ ASM_PFX(OnStmSetup) 59 DQ ASM_PFX(OnStmTeardown) 60 DQ 0 ; SmmSmiHandlerRip - SMM guest entrypoint 61 DQ 0 ; SmmSmiHandlerRsp 62 DQ 0 63 DD 0 64 DD 0x80010100 ; RequiredStmSmmRevId 65 DQ ASM_PFX(OnException) 66 DQ 0 ; ExceptionStack 67 DW DATA_SEL 68 DW 0x01F ; ExceptionFilter 69 DD 0 70 DQ 0 71 DQ 0 ; BiosHwResourceRequirementsPtr 72 DQ 0 ; AcpiRsdp 73 DB 0 ; PhysicalAddressBits 74PSD_SIZE equ $ - ASM_PFX(gcStmPsd) 75 76 DEFAULT REL 77 SECTION .text 78;------------------------------------------------------------------------------ 79; SMM Exception handlers 80;------------------------------------------------------------------------------ 81global ASM_PFX(OnException) 82ASM_PFX(OnException): 83 mov rcx, rsp 84 add rsp, -0x28 85 call ASM_PFX(SmmStmExceptionHandler) 86 add rsp, 0x28 87 mov ebx, eax 88 mov eax, 4 89 DB 0x0f, 0x01, 0x0c1 ; VMCALL 90 jmp $ 91 92global ASM_PFX(OnStmSetup) 93ASM_PFX(OnStmSetup): 94; 95; Check XD disable bit 96; 97 xor r8, r8 98 mov rax, ASM_PFX(gStmXdSupported) 99 mov al, [rax] 100 cmp al, 0 101 jz @StmXdDone1 102 mov ecx, MSR_IA32_MISC_ENABLE 103 rdmsr 104 mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32] 105 test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34] 106 jz .01 107 and dx, 0xFFFB ; clear XD Disable bit if it is set 108 wrmsr 109.01: 110 mov ecx, MSR_EFER 111 rdmsr 112 or ax, MSR_EFER_XD ; enable NXE 113 wrmsr 114@StmXdDone1: 115 push r8 116 117 add rsp, -0x20 118 call ASM_PFX(SmmStmSetup) 119 add rsp, 0x20 120 121 mov rax, ASM_PFX(gStmXdSupported) 122 mov al, [rax] 123 cmp al, 0 124 jz .11 125 pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32] 126 test edx, BIT2 127 jz .11 128 mov ecx, MSR_IA32_MISC_ENABLE 129 rdmsr 130 or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM 131 wrmsr 132 133.11: 134 rsm 135 136global ASM_PFX(OnStmTeardown) 137ASM_PFX(OnStmTeardown): 138; 139; Check XD disable bit 140; 141 xor r8, r8 142 mov rax, ASM_PFX(gStmXdSupported) 143 mov al, [rax] 144 cmp al, 0 145 jz @StmXdDone2 146 mov ecx, MSR_IA32_MISC_ENABLE 147 rdmsr 148 mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32] 149 test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34] 150 jz .02 151 and dx, 0xFFFB ; clear XD Disable bit if it is set 152 wrmsr 153.02: 154 mov ecx, MSR_EFER 155 rdmsr 156 or ax, MSR_EFER_XD ; enable NXE 157 wrmsr 158@StmXdDone2: 159 push r8 160 161 add rsp, -0x20 162 call ASM_PFX(SmmStmTeardown) 163 add rsp, 0x20 164 165 mov rax, ASM_PFX(gStmXdSupported) 166 mov al, [rax] 167 cmp al, 0 168 jz .12 169 pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32] 170 test edx, BIT2 171 jz .12 172 mov ecx, MSR_IA32_MISC_ENABLE 173 rdmsr 174 or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM 175 wrmsr 176 177.12: 178 rsm 179 180