1/**************************************************************************; 2;* *; 3;* *; 4;* Intel Corporation - ACPI Reference Code for the Baytrail *; 5;* Family of Customer Reference Boards. *; 6;* *; 7;* *; 8;* Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved *; 9; 10; This program and the accompanying materials are licensed and made available under 11; the terms and conditions of the BSD License that accompanies this distribution. 12; The full text of the license may be found at 13; http://opensource.org/licenses/bsd-license.php. 14; 15; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 16; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 17; 18;* *; 19;* *; 20;**************************************************************************/ 21 22 23 24// Define a Global region of ACPI NVS Region that may be used for any 25// type of implementation. The starting offset and size will be fixed 26// up by the System BIOS during POST. Note that the Size must be a word 27// in size to be fixed up correctly. 28 29OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55) 30Field(GNVS,AnyAcc,Lock,Preserve) 31{ 32 Offset(0), // Miscellaneous Dynamic Registers: 33 OSYS, 16, // (00) Operating System 34 , 8, // (02) 35 , 8, // (03) 36 , 8, // (04) 37 , 8, // (05) 38 , 8, // (06) 39 , 8, // (07) 40 , 8, // (08) 41 , 8, // (09) 42 , 8, // (10) 43 P80D, 32, // (11) Port 80 Debug Port Value 44 LIDS, 8, // (15) Lid State (Lid Open = 1) 45 , 8, // (16) 46 , 8, // (17) 47 Offset(18), // Thermal Policy Registers: 48 , 8, // (18) 49 , 8, // (19) 50 ACTT, 8, // (20) Active Trip Point 51 PSVT, 8, // (21) Passive Trip Point 52 TC1V, 8, // (22) Passive Trip Point TC1 Value 53 TC2V, 8, // (23) Passive Trip Point TC2 Value 54 TSPV, 8, // (24) Passive Trip Point TSP Value 55 CRTT, 8, // (25) Critical Trip Point 56 DTSE, 8, // (26) Digital Thermal Sensor Enable 57 DTS1, 8, // (27) Digital Thermal Sensor 1 Reading 58 DTS2, 8, // (28) Digital Thermal Sensor 2 Reading 59 DTSF, 8, // (29) DTS SMI Function Call 60 Offset(30), // Battery Support Registers: 61 , 8, // (30) 62 , 8, // (31) 63 , 8, // (32) 64 , 8, // (33) 65 , 8, // (34) 66 , 8, // (35) 67 , 8, // (36) 68 Offset(40), // CPU Identification Registers: 69 APIC, 8, // (40) APIC Enabled by SBIOS (APIC Enabled = 1) 70 MPEN, 8, // (41) Number of Logical Processors if MP Enabled != 0 71 , 8, // (42) 72 , 8, // (43) 73 , 8, // (44) 74 , 32, // (45) 75 Offset(50), // SIO CMOS Configuration Registers: 76 , 8, // (50) 77 , 8, // (51) 78 , 8, // (52) 79 , 8, // (53) 80 , 8, // (54) 81 , 8, // (55) 82 , 8, // (56) 83 , 8, // (57) 84 , 8, // (58) 85 Offset(60), // Internal Graphics Registers: 86 , 8, // (60) 87 , 8, // (61) 88 CADL, 8, // (62) Current Attached Device List 89 , 8, // (63) 90 CSTE, 16, // (64) Current Display State 91 NSTE, 16, // (66) Next Display State 92 , 16, // (68) 93 NDID, 8, // (70) Number of Valid Device IDs 94 DID1, 32, // (71) Device ID 1 95 DID2, 32, // (75) Device ID 2 96 DID3, 32, // (79) Device ID 3 97 DID4, 32, // (83) Device ID 4 98 DID5, 32, // (87) Device ID 5 99 , 32, // (91) 100 , 8, // (95) Fifth byte of AKSV (mannufacturing mode) 101 Offset(103), // Backlight Control Registers: 102 , 8, // (103) 103 BRTL, 8, // (104) Brightness Level Percentage 104 Offset(105), // Ambiant Light Sensor Registers: 105 , 8, // (105) 106 , 8, // (106) 107 LLOW, 8, // (107) LUX Low Value 108 , 8, // (108) 109 Offset(110), // EMA Registers: 110 , 8, // (110) 111 , 16, // (111) 112 , 16, // (113) 113 Offset(116), // MEF Registers: 114 , 8, // (116) MEF Enable 115 Offset(117), // PCIe Dock: 116 , 8, // (117) 117 Offset(120), // TPM Registers: 118 , 8, // (120) 119 , 8, // (121) 120 , 8, // (122) 121 , 8, // (123) 122 , 32, // (124) 123 , 8, // (125) 124 , 8, // (129) 125 Offset(130), // 126 , 56, // (130) 127 , 56, // (137) 128 , 8, // (144) 129 , 56, // (145) 130 Offset(170), // IGD OpRegion/Software SCI base address 131 ASLB, 32, // (170) IGD OpRegion base address 132 Offset(174), // IGD OpRegion/Software SCI shared data 133 IBTT, 8, // (174) IGD Boot Display Device 134 IPAT, 8, // (175) IGD Panel Type CMOs option 135 ITVF, 8, // (176) IGD TV Format CMOS option 136 ITVM, 8, // (177) IGD TV Minor Format CMOS option 137 IPSC, 8, // (178) IGD Panel Scaling 138 IBLC, 8, // (179) IGD BLC Configuration 139 IBIA, 8, // (180) IGD BIA Configuration 140 ISSC, 8, // (181) IGD SSC Configuration 141 I409, 8, // (182) IGD 0409 Modified Settings Flag 142 I509, 8, // (183) IGD 0509 Modified Settings Flag 143 I609, 8, // (184) IGD 0609 Modified Settings Flag 144 I709, 8, // (185) IGD 0709 Modified Settings Flag 145 IDMM, 8, // (186) IGD DVMT Mode 146 IDMS, 8, // (187) IGD DVMT Memory Size 147 IF1E, 8, // (188) IGD Function 1 Enable 148 HVCO, 8, // (189) HPLL VCO 149 NXD1, 32, // (190) Next state DID1 for _DGS 150 NXD2, 32, // (194) Next state DID2 for _DGS 151 NXD3, 32, // (198) Next state DID3 for _DGS 152 NXD4, 32, // (202) Next state DID4 for _DGS 153 NXD5, 32, // (206) Next state DID5 for _DGS 154 NXD6, 32, // (210) Next state DID6 for _DGS 155 NXD7, 32, // (214) Next state DID7 for _DGS 156 NXD8, 32, // (218) Next state DID8 for _DGS 157 GSMI, 8, // (222) GMCH SMI/SCI mode (0=SCI) 158 PAVP, 8, // (223) IGD PAVP data 159 Offset(225), 160 OSCC, 8, // (225) PCIE OSC Control 161 NEXP, 8, // (226) Native PCIE Setup Value 162 Offset(235), // Global Variables 163 DSEN, 8, // (235) _DOS Display Support Flag. 164 ECON, 8, // (236) Embedded Controller Availability Flag. 165 GPIC, 8, // (237) Global IOAPIC/8259 Interrupt Mode Flag. 166 CTYP, 8, // (238) Global Cooling Type Flag. 167 L01C, 8, // (239) Global L01 Counter. 168 VFN0, 8, // (240) Virtual Fan0 Status. 169 VFN1, 8, // (241) Virtual Fan1 Status. 170 Offset(256), 171 NVGA, 32, // (256) NVIG opregion address 172 NVHA, 32, // (260) NVHM opregion address 173 AMDA, 32, // (264) AMDA opregion address 174 DID6, 32, // (268) Device ID 6 175 DID7, 32, // (272) Device ID 7 176 DID8, 32, // (276) Device ID 8 177 Offset(332), 178 USEL, 8, // (332) UART Selection 179 PU1E, 8, // (333) PCU UART 1 Enabled 180 PU2E, 8, // (334) PCU UART 2 Enabled 181 182 LPE0, 32, // (335) LPE Bar0 183 LPE1, 32, // (339) LPE Bar1 184 LPE2, 32, // (343) LPE Bar2 185 186 Offset(347), 187 , 8, // (347) 188 , 8, // (348) 189 PFLV, 8, // (349) Platform Flavor 190 191 Offset(351), 192 ICNF, 8, // (351) ISCT / AOAC Configuration 193 XHCI, 8, // (352) xHCI controller mode 194 PMEN, 8, // (353) PMIC enable/disable 195 196 LPEE, 8, // (354) LPE enable/disable 197 ISPA, 32, // (355) ISP Base Addr 198 ISPD, 8, // (359) ISP Device Selection 0: Disabled; 1: PCI Device 2; 2: PCI Device 3 199 200 offset(360), // ((4+8+6)*4+2)*4=296 201 // 202 // Lpss controllers 203 // 204 PCIB, 32, 205 PCIT, 32, 206 D10A, 32, //DMA1 207 D10L, 32, 208 D11A, 32, 209 D11L, 32, 210 P10A, 32, // PWM1 211 P10L, 32, 212 P11A, 32, 213 P11L, 32, 214 P20A, 32, // PWM2 215 P20L, 32, 216 P21A, 32, 217 P21L, 32, 218 U10A, 32, // UART1 219 U10L, 32, 220 U11A, 32, 221 U11L, 32, 222 U20A, 32, // UART2 223 U20L, 32, 224 U21A, 32, 225 U21L, 32, 226 SP0A, 32, // SPI 227 SP0L, 32, 228 SP1A, 32, 229 SP1L, 32, 230 231 D20A, 32, //DMA2 232 D20L, 32, 233 D21A, 32, 234 D21L, 32, 235 I10A, 32, // I2C1 236 I10L, 32, 237 I11A, 32, 238 I11L, 32, 239 I20A, 32, // I2C2 240 I20L, 32, 241 I21A, 32, 242 I21L, 32, 243 I30A, 32, // I2C3 244 I30L, 32, 245 I31A, 32, 246 I31L, 32, 247 I40A, 32, // I2C4 248 I40L, 32, 249 I41A, 32, 250 I41L, 32, 251 I50A, 32, // I2C5 252 I50L, 32, 253 I51A, 32, 254 I51L, 32, 255 I60A, 32, // I2C6 256 I60L, 32, 257 I61A, 32, 258 I61L, 32, 259 I70A, 32, // I2C7 260 I70L, 32, 261 I71A, 32, 262 I71L, 32, 263 // 264 // Scc controllers 265 // 266 eM0A, 32, // EMMC 267 eM0L, 32, 268 eM1A, 32, 269 eM1L, 32, 270 SI0A, 32, // SDIO 271 SI0L, 32, 272 SI1A, 32, 273 SI1L, 32, 274 SD0A, 32, // SDCard 275 SD0L, 32, 276 SD1A, 32, 277 SD1L, 32, 278 MH0A, 32, // 279 MH0L, 32, 280 MH1A, 32, 281 MH1L, 32, 282 283 offset(656), 284 SDRM, 8, 285 offset(657), 286 HLPS, 8, //(657) Hide Devices 287 offset(658), 288 OSEL, 8, //(658) OS Seletion - Windows/Android 289 290 offset(659), // VLV1 DPTF 291 SDP1, 8, //(659) An enumerated value corresponding to SKU 292 DPTE, 8, //(660) DPTF Enable 293 THM0, 8, //(661) System Thermal 0 294 THM1, 8, //(662) System Thermal 1 295 THM2, 8, //(663) System Thermal 2 296 THM3, 8, //(664) System Thermal 3 297 THM4, 8, //(665) System Thermal 3 298 CHGR, 8, //(666) DPTF Changer Device 299 DDSP, 8, //(667) DPTF Display Device 300 DSOC, 8, //(668) DPTF SoC device 301 DPSR, 8, //(669) DPTF Processor device 302 DPCT, 32, //(670) DPTF Processor participant critical temperature 303 DPPT, 32, //(674) DPTF Processor participant passive temperature 304 DGC0, 32, //(678) DPTF Generic sensor0 participant critical temperature 305 DGP0, 32, //(682) DPTF Generic sensor0 participant passive temperature 306 DGC1, 32, //(686) DPTF Generic sensor1 participant critical temperature 307 DGP1, 32, //(690) DPTF Generic sensor1 participant passive temperature 308 DGC2, 32, //(694) DPTF Generic sensor2 participant critical temperature 309 DGP2, 32, //(698) DPTF Generic sensor2 participant passive temperature 310 DGC3, 32, //(702) DPTF Generic sensor3 participant critical temperature 311 DGP3, 32, //(706) DPTF Generic sensor3 participant passive temperature 312 DGC4, 32, //(710)DPTF Generic sensor3 participant critical temperature 313 DGP4, 32, //(714)DPTF Generic sensor3 participant passive temperature 314 DLPM, 8, //(718) DPTF Current low power mode setting 315 DSC0, 32, //(719) DPTF Critical threshold0 for SCU 316 DSC1, 32, //(723) DPTF Critical threshold1 for SCU 317 DSC2, 32, //(727) DPTF Critical threshold2 for SCU 318 DSC3, 32, //(731) DPTF Critical threshold3 for SCU 319 DSC4, 32, //(735) DPTF Critical threshold3 for SCU 320 DDBG, 8, //(739) DPTF Super Debug option. 0 - Disabled, 1 - Enabled 321 LPOE, 32, //(740) DPTF LPO Enable 322 LPPS, 32, //(744) P-State start index 323 LPST, 32, //(748) Step size 324 LPPC, 32, //(752) Power control setting 325 LPPF, 32, //(756) Performance control setting 326 DPME, 8, //(760) DPTF DPPM enable/disable 327 BCSL, 8, //(761) Battery charging solution 0-CLV 1-ULPMC 328 NFCS, 8, //(762) NFCx Select 1: NFC1 2:NFC2 329 PCIM, 8, //(763) EMMC device 0-ACPI mode, 1-PCI mode 330 TPMA, 32, //(764) 331 TPML, 32, //(768) 332 ITSA, 8, //(772) I2C Touch Screen Address 333 S0IX, 8, //(773) S0ix status 334 SDMD, 8, //(774) SDIO Mode 335 EMVR, 8, //(775) eMMC controller version 336 BMBD, 32, //(776) BM Bound 337 FSAS, 8, //(780) FSA Status 338 BDID, 8, //(781) Board ID 339 FBID, 8, //(782) FAB ID 340 OTGM, 8, //(783) OTG mode 341 STEP, 8, //(784) Stepping ID 342 WITT, 8, //(785) Enable Test Device connected to I2C for WHCK test. 343 SOCS, 8, //(786) provide the SoC stepping infomation 344 AMTE, 8, //(787) Ambient Trip point change 345 UTS, 8, //(788) Enable Test Device connected to URT for WHCK test. 346 SCPE, 8, //(789) Allow higher performance on AC/USB - Enable/Disable 347 Offset(792), 348 EDPV, 8, //(792) Check for eDP display device 349 DIDX, 32, //(793) Device ID for eDP device 350 IOT, 8, //(794) MinnowBoard Max JP1 is configured for MSFT IOT project. 351 BATT, 8, //(795) The Flag of RTC Battery Prensent. 352 LPAD, 8, //(796) 353} 354 355