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1 /** @file
2 
3   Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
4 
5 
6   This program and the accompanying materials are licensed and made available under
7 
8   the terms and conditions of the BSD License that accompanies this distribution.
9 
10   The full text of the license may be found at
11 
12   http://opensource.org/licenses/bsd-license.php.
13 
14 
15 
16   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17 
18   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 
20 
21 
22 
23 Module Name:
24 
25     SioInit.c
26 
27 Abstract:
28 
29     Functions for LpcSio initialization
30 
31 --*/
32 
33 #include "PlatformSerialPortLib.h"
34 #include "SioInit.h"
35 
36 typedef struct {
37   UINT8 Register;
38   UINT8 Value;
39 } EFI_SIO_TABLE;
40 
41 EFI_SIO_TABLE mSioTableWpcn381u[] = {
42     {0x29, 0x0A0},
43     {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0},                                       // Select UART0 device
44     {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)},       // Set Base Address MSB
45     {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)},   // Set Base Address LSB
46     {WPCN381U_IRQ1_REGISTER, 0x014},                                                      // Set to IRQ4
47     {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit
48     {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1},                                       // Select UART1 device
49     {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)},       // Set Base Address MSB
50     {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)},   // Set Base Address LSB
51     {WPCN381U_IRQ1_REGISTER, 0x013},                                                      // Set to IRQ3
52     {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit
53     {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO},                                        // Select GPIO device
54     {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)},               // Set Base Address MSB
55     {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)},           // Set Base Address LSB
56     {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit
57     {0x21, 0x001},                                                                        // Global Device Enable
58     {0x26, 0x000}
59 };
60 
61 EFI_SIO_TABLE mSioTableWdcp376[] = {
62     {0x29, 0x0A0},
63     {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0},                                       // Select UART0 device
64     {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)},       // Set Base Address MSB
65     {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)},   // Set Base Address LSB
66     {WPCN381U_IRQ1_REGISTER, 0x014},                                                      // Set to IRQ4
67     {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit
68     {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1},                                       // Select UART1 device
69     {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)},       // Set Base Address MSB
70     {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)},   // Set Base Address LSB
71     {WPCN381U_IRQ1_REGISTER, 0x013},                                                      // Set to IRQ3
72     {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit
73     {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO},                                        // Select GPIO device
74     {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)},               // Set Base Address MSB
75     {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)},           // Set Base Address LSB
76     {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit
77     {0x21, 0x001},                                                                        // Global Device Enable
78     {0x26, 0x000},
79     {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2K},                                        // Select PS2 Keyboard
80     {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS >> 8)},                // Set Base Address MSB
81     {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS & 0x00FF)},            // Set Base Address LSB
82     {WPCN381U_BASE2_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS >> 8)},                // Set Base Address MSB
83     {WPCN381U_BASE2_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS & 0x00FF)},            // Set Base Address LSB
84     {WPCN381U_IRQ1_REGISTER, 0x011},                                                      // Set to IRQ1
85     {0xF0, (SIO_KBC_CLOCK << 6)},                                                         // Select KBC Clock Source
86     {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit
87     {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2M},                                        // Select PS2 Mouse
88     {WPCN381U_IRQ1_REGISTER, 0x01c},                                                      // Set to IRQ12
89     {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}                                 // Enable it with Activation bit
90 };
91 
92 /**
InitializeSio(VOID)93   Initialization for SIO.
94 
95   @param FfsHeader     FV this PEIM was loaded from.
96   @param PeiServices   General purpose services available to every PEIM.
97 
98   None
99 
100 **/
101 VOID
102 InitializeSio (
103   VOID
104   )
105 {
106   UINT16          Index;
107   UINT16          IndexPort;
108   UINT16          DataPort;
109 
110   //
111   // Super I/O initialization for Winbond WPCN381U
112   //
113   IndexPort  = WPCN381U_CONFIG_INDEX;
114   DataPort   = WPCN381U_CONFIG_DATA;
115 
116   //
117   // Check for Winbond WPCN381U
118   //
119   IoWrite8 (IndexPort, WPCN381U_DEV_ID_REGISTER);   // Winbond WPCN381U Device ID register is 0x20
120 
121   if (IoRead8 (DataPort) == WPCN381U_CHIP_ID) {   // Winbond WPCN381U Device ID is 0xF4
122     //
123     // Configure WPCN381U SIO
124     //
125     for (Index = 0; Index < sizeof (mSioTableWpcn381u) / sizeof (EFI_SIO_TABLE); Index++) {
126       IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register);
127       IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value);
128     }
129   }
130 
131   if (IoRead8 (DataPort) == WDCP376_CHIP_ID) {   // Winbond WDCP376 Device ID is 0xF1
132     //
133     // Configure WDCP376 SIO
134     //
135     for (Index = 0; Index < sizeof (mSioTableWdcp376) / sizeof (EFI_SIO_TABLE); Index++) {
136       IoWrite8 (IndexPort, mSioTableWdcp376[Index].Register);
137       IoWrite8 (DataPort, mSioTableWdcp376[Index].Value);
138     }
139   }
140   return;
141 }
142