1 // Auto-generated file. Do not edit!
2 // Template: src/f32-dwconv/up-avx.c.in
3 // Generator: tools/xngen
4 //
5 // Copyright 2019 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9
10 #include <assert.h>
11
12 #include <immintrin.h>
13
14 #include <xnnpack/dwconv.h>
15
16
17 static const int32_t mask_table[14] = {-1, -1, -1, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0};
18
xnn_f32_dwconv_ukernel_up16x4__avx_acc2(size_t channels,size_t output_width,const float ** input,const float * weights,float * output,size_t input_stride,size_t output_increment,const union xnn_f32_output_params params[restrict static1])19 void xnn_f32_dwconv_ukernel_up16x4__avx_acc2(
20 size_t channels,
21 size_t output_width,
22 const float** input,
23 const float* weights,
24 float* output,
25 size_t input_stride,
26 size_t output_increment,
27 const union xnn_f32_output_params params[restrict static 1])
28 {
29 assert(channels != 0);
30 assert(output_width != 0);
31
32 const __m256 vmax = _mm256_broadcast_ps((const __m128*) params->sse.max);
33 const __m256 vmin = _mm256_broadcast_ps((const __m128*) params->sse.min);
34 do {
35 const float* i0 = input[0];
36 assert(i0 != NULL);
37 const float* i1 = input[1];
38 assert(i1 != NULL);
39 const float* i2 = input[2];
40 assert(i2 != NULL);
41 const float* i3 = input[3];
42 assert(i3 != NULL);
43 input = (const float**) ((uintptr_t) input + input_stride);
44
45 size_t c = channels;
46 const float* w = weights;
47 for (; c >= 16; c -= 16) {
48 __m256 vacc01234567p0 = _mm256_load_ps(w);
49 __m256 vacc89ABCDEFp0 = _mm256_load_ps(w + 8);
50
51
52 const __m256 vi0x01234567 = _mm256_loadu_ps(i0);
53 const __m256 vi0x89ABCDEF = _mm256_loadu_ps(i0 + 8);
54 i0 += 16;
55
56 const __m256 vk0x01234567 = _mm256_load_ps(w + 16);
57 const __m256 vk0x89ABCDEF = _mm256_load_ps(w + 24);
58 vacc01234567p0 = _mm256_add_ps(vacc01234567p0, _mm256_mul_ps(vi0x01234567, vk0x01234567));
59 vacc89ABCDEFp0 = _mm256_add_ps(vacc89ABCDEFp0, _mm256_mul_ps(vi0x89ABCDEF, vk0x89ABCDEF));
60
61 const __m256 vi1x01234567 = _mm256_loadu_ps(i1);
62 const __m256 vi1x89ABCDEF = _mm256_loadu_ps(i1 + 8);
63 i1 += 16;
64
65 const __m256 vk1x01234567 = _mm256_load_ps(w + 32);
66 const __m256 vk1x89ABCDEF = _mm256_load_ps(w + 40);
67 __m256 vacc01234567p1 = _mm256_mul_ps(vi1x01234567, vk1x01234567);
68 __m256 vacc89ABCDEFp1 = _mm256_mul_ps(vi1x89ABCDEF, vk1x89ABCDEF);
69
70 const __m256 vi2x01234567 = _mm256_loadu_ps(i2);
71 const __m256 vi2x89ABCDEF = _mm256_loadu_ps(i2 + 8);
72 i2 += 16;
73
74 const __m256 vk2x01234567 = _mm256_load_ps(w + 48);
75 const __m256 vk2x89ABCDEF = _mm256_load_ps(w + 56);
76 vacc01234567p0 = _mm256_add_ps(vacc01234567p0, _mm256_mul_ps(vi2x01234567, vk2x01234567));
77 vacc89ABCDEFp0 = _mm256_add_ps(vacc89ABCDEFp0, _mm256_mul_ps(vi2x89ABCDEF, vk2x89ABCDEF));
78
79 const __m256 vi3x01234567 = _mm256_loadu_ps(i3);
80 const __m256 vi3x89ABCDEF = _mm256_loadu_ps(i3 + 8);
81 i3 += 16;
82
83 const __m256 vk3x01234567 = _mm256_load_ps(w + 64);
84 const __m256 vk3x89ABCDEF = _mm256_load_ps(w + 72);
85 vacc01234567p1 = _mm256_add_ps(vacc01234567p1, _mm256_mul_ps(vi3x01234567, vk3x01234567));
86 vacc89ABCDEFp1 = _mm256_add_ps(vacc89ABCDEFp1, _mm256_mul_ps(vi3x89ABCDEF, vk3x89ABCDEF));
87
88 w += 80;
89
90 // Add up all accumulators to vacc0123456789ABCDEFp0
91 vacc01234567p0 = _mm256_add_ps(vacc01234567p0, vacc01234567p1);
92 vacc89ABCDEFp0 = _mm256_add_ps(vacc89ABCDEFp0, vacc89ABCDEFp1);
93
94 __m256 vacc01234567 = _mm256_max_ps(vacc01234567p0, vmin);
95 __m256 vacc89ABCDEF = _mm256_max_ps(vacc89ABCDEFp0, vmin);
96 vacc01234567 = _mm256_min_ps(vacc01234567, vmax);
97 vacc89ABCDEF = _mm256_min_ps(vacc89ABCDEF, vmax);
98
99 _mm256_storeu_ps(output, vacc01234567);
100 _mm256_storeu_ps(output + 8, vacc89ABCDEF);
101 output += 16;
102 }
103 for (; c >= 8; c -= 8) {
104 __m256 vacc01234567p0 = _mm256_load_ps(w);
105
106 const __m256 vi0x01234567 = _mm256_loadu_ps(i0);
107 i0 += 8;
108
109 const __m256 vk0x01234567 = _mm256_load_ps(w + 16);
110 vacc01234567p0 = _mm256_add_ps(vacc01234567p0, _mm256_mul_ps(vi0x01234567, vk0x01234567));
111
112 const __m256 vi1x01234567 = _mm256_loadu_ps(i1);
113 i1 += 8;
114
115 const __m256 vk1x01234567 = _mm256_load_ps(w + 32);
116 __m256 vacc01234567p1 = _mm256_mul_ps(vi1x01234567, vk1x01234567);
117
118 const __m256 vi2x01234567 = _mm256_loadu_ps(i2);
119 i2 += 8;
120
121 const __m256 vk2x01234567 = _mm256_load_ps(w + 48);
122 vacc01234567p0 = _mm256_add_ps(vacc01234567p0, _mm256_mul_ps(vi2x01234567, vk2x01234567));
123
124 const __m256 vi3x01234567 = _mm256_loadu_ps(i3);
125 i3 += 8;
126
127 const __m256 vk3x01234567 = _mm256_load_ps(w + 64);
128 vacc01234567p1 = _mm256_add_ps(vacc01234567p1, _mm256_mul_ps(vi3x01234567, vk3x01234567));
129
130 w += 8;
131
132 // Add up all accumulators to vacc01234567p0
133 vacc01234567p0 = _mm256_add_ps(vacc01234567p0, vacc01234567p1);
134
135 __m256 vacc01234567 = _mm256_max_ps(vacc01234567p0, vmin);
136 vacc01234567 = _mm256_min_ps(vacc01234567, vmax);
137
138 _mm256_storeu_ps(output, vacc01234567);
139 output += 8;
140 }
141 if XNN_UNLIKELY(c != 0) {
142 assert(c >= 1);
143 assert(c <= 7);
144 __m256i vmask = _mm256_loadu_si256((const __m256i*) &mask_table[7 - c]);
145
146 __m256 vacc01234567p0 = _mm256_load_ps(w);
147
148 const __m256 vi0x01234567 = _mm256_maskload_ps(i0, vmask);
149 const __m256 vk0x01234567 = _mm256_load_ps(w + 16);
150 vacc01234567p0 = _mm256_add_ps(vacc01234567p0, _mm256_mul_ps(vi0x01234567, vk0x01234567));
151
152 const __m256 vi1x01234567 = _mm256_maskload_ps(i1, vmask);
153 const __m256 vk1x01234567 = _mm256_load_ps(w + 32);
154 __m256 vacc01234567p1 = _mm256_mul_ps(vi1x01234567, vk1x01234567);
155
156 const __m256 vi2x01234567 = _mm256_maskload_ps(i2, vmask);
157 const __m256 vk2x01234567 = _mm256_load_ps(w + 48);
158 vacc01234567p0 = _mm256_add_ps(vacc01234567p0, _mm256_mul_ps(vi2x01234567, vk2x01234567));
159
160 const __m256 vi3x01234567 = _mm256_maskload_ps(i3, vmask);
161 const __m256 vk3x01234567 = _mm256_load_ps(w + 64);
162 vacc01234567p1 = _mm256_add_ps(vacc01234567p1, _mm256_mul_ps(vi3x01234567, vk3x01234567));
163
164 // Add up all accumulators to vacc01234567p0
165 vacc01234567p0 = _mm256_add_ps(vacc01234567p0, vacc01234567p1);
166
167 __m256 vacc01234567 = _mm256_max_ps(vacc01234567p0, vmin);
168 vacc01234567 = _mm256_min_ps(vacc01234567, vmax);
169
170 // _mm256_maskstore_ps(output, vmask, vacc01234567); output += c; could be used here, but triggers msan failures (probably an msan bug).
171 __m128 vacc0123 = _mm256_castps256_ps128(vacc01234567);
172 if (c & 4) {
173 _mm_storeu_ps(output, vacc0123);
174 vacc0123 = _mm256_extractf128_ps(vacc01234567, 1);
175 output += 4;
176 }
177 if (c & 2) {
178 _mm_storel_pi((__m64*) output, vacc0123);
179 vacc0123 = _mm_movehl_ps(vacc0123, vacc0123);
180 output += 2;
181 }
182 if (c & 1) {
183 _mm_store_ss(output, vacc0123);
184 output += 1;
185 }
186 }
187
188 output = (float*) ((uintptr_t) output + output_increment);
189 } while (--output_width != 0);
190 }
191