1 // Auto-generated file. Do not edit!
2 // Template: src/f32-dwconv/up-avx.c.in
3 // Generator: tools/xngen
4 //
5 // Copyright 2019 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9
10 #include <assert.h>
11
12 #include <immintrin.h>
13
14 #include <xnnpack/dwconv.h>
15
16
17 static const int32_t mask_table[14] = {-1, -1, -1, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0};
18
xnn_f32_dwconv_ukernel_up16x9__fma3_acc2(size_t channels,size_t output_width,const float ** input,const float * weights,float * output,size_t input_stride,size_t output_increment,const union xnn_f32_output_params params[restrict static1])19 void xnn_f32_dwconv_ukernel_up16x9__fma3_acc2(
20 size_t channels,
21 size_t output_width,
22 const float** input,
23 const float* weights,
24 float* output,
25 size_t input_stride,
26 size_t output_increment,
27 const union xnn_f32_output_params params[restrict static 1])
28 {
29 assert(channels != 0);
30 assert(output_width != 0);
31
32 const __m256 vmax = _mm256_broadcast_ps((const __m128*) params->sse.max);
33 const __m256 vmin = _mm256_broadcast_ps((const __m128*) params->sse.min);
34 do {
35 const float* i0 = input[0];
36 assert(i0 != NULL);
37 const float* i1 = input[1];
38 assert(i1 != NULL);
39 const float* i2 = input[2];
40 assert(i2 != NULL);
41 const float* i3 = input[3];
42 assert(i3 != NULL);
43 const float* i4 = input[4];
44 assert(i4 != NULL);
45 const float* i5 = input[5];
46 assert(i5 != NULL);
47 const float* i6 = input[6];
48 assert(i6 != NULL);
49 const float* i7 = input[7];
50 assert(i7 != NULL);
51 const float* i8 = input[8];
52 assert(i8 != NULL);
53 input = (const float**) ((uintptr_t) input + input_stride);
54
55 size_t c = channels;
56 const float* w = weights;
57 for (; c >= 16; c -= 16) {
58 __m256 vacc01234567p0 = _mm256_load_ps(w);
59 __m256 vacc89ABCDEFp0 = _mm256_load_ps(w + 8);
60
61
62 const __m256 vi0x01234567 = _mm256_loadu_ps(i0);
63 const __m256 vi0x89ABCDEF = _mm256_loadu_ps(i0 + 8);
64 i0 += 16;
65
66 const __m256 vk0x01234567 = _mm256_load_ps(w + 16);
67 const __m256 vk0x89ABCDEF = _mm256_load_ps(w + 24);
68 vacc01234567p0 = _mm256_fmadd_ps(vi0x01234567, vk0x01234567, vacc01234567p0);
69 vacc89ABCDEFp0 = _mm256_fmadd_ps(vi0x89ABCDEF, vk0x89ABCDEF, vacc89ABCDEFp0);
70
71 const __m256 vi1x01234567 = _mm256_loadu_ps(i1);
72 const __m256 vi1x89ABCDEF = _mm256_loadu_ps(i1 + 8);
73 i1 += 16;
74
75 const __m256 vk1x01234567 = _mm256_load_ps(w + 32);
76 const __m256 vk1x89ABCDEF = _mm256_load_ps(w + 40);
77 __m256 vacc01234567p1 = _mm256_mul_ps(vi1x01234567, vk1x01234567);
78 __m256 vacc89ABCDEFp1 = _mm256_mul_ps(vi1x89ABCDEF, vk1x89ABCDEF);
79
80 const __m256 vi2x01234567 = _mm256_loadu_ps(i2);
81 const __m256 vi2x89ABCDEF = _mm256_loadu_ps(i2 + 8);
82 i2 += 16;
83
84 const __m256 vk2x01234567 = _mm256_load_ps(w + 48);
85 const __m256 vk2x89ABCDEF = _mm256_load_ps(w + 56);
86 vacc01234567p0 = _mm256_fmadd_ps(vi2x01234567, vk2x01234567, vacc01234567p0);
87 vacc89ABCDEFp0 = _mm256_fmadd_ps(vi2x89ABCDEF, vk2x89ABCDEF, vacc89ABCDEFp0);
88
89 const __m256 vi3x01234567 = _mm256_loadu_ps(i3);
90 const __m256 vi3x89ABCDEF = _mm256_loadu_ps(i3 + 8);
91 i3 += 16;
92
93 const __m256 vk3x01234567 = _mm256_load_ps(w + 64);
94 const __m256 vk3x89ABCDEF = _mm256_load_ps(w + 72);
95 vacc01234567p1 = _mm256_fmadd_ps(vi3x01234567, vk3x01234567, vacc01234567p1);
96 vacc89ABCDEFp1 = _mm256_fmadd_ps(vi3x89ABCDEF, vk3x89ABCDEF, vacc89ABCDEFp1);
97
98 const __m256 vi4x01234567 = _mm256_loadu_ps(i4);
99 const __m256 vi4x89ABCDEF = _mm256_loadu_ps(i4 + 8);
100 i4 += 16;
101
102 const __m256 vk4x01234567 = _mm256_load_ps(w + 80);
103 const __m256 vk4x89ABCDEF = _mm256_load_ps(w + 88);
104 vacc01234567p0 = _mm256_fmadd_ps(vi4x01234567, vk4x01234567, vacc01234567p0);
105 vacc89ABCDEFp0 = _mm256_fmadd_ps(vi4x89ABCDEF, vk4x89ABCDEF, vacc89ABCDEFp0);
106
107 const __m256 vi5x01234567 = _mm256_loadu_ps(i5);
108 const __m256 vi5x89ABCDEF = _mm256_loadu_ps(i5 + 8);
109 i5 += 16;
110
111 const __m256 vk5x01234567 = _mm256_load_ps(w + 96);
112 const __m256 vk5x89ABCDEF = _mm256_load_ps(w + 104);
113 vacc01234567p1 = _mm256_fmadd_ps(vi5x01234567, vk5x01234567, vacc01234567p1);
114 vacc89ABCDEFp1 = _mm256_fmadd_ps(vi5x89ABCDEF, vk5x89ABCDEF, vacc89ABCDEFp1);
115
116 const __m256 vi6x01234567 = _mm256_loadu_ps(i6);
117 const __m256 vi6x89ABCDEF = _mm256_loadu_ps(i6 + 8);
118 i6 += 16;
119
120 const __m256 vk6x01234567 = _mm256_load_ps(w + 112);
121 const __m256 vk6x89ABCDEF = _mm256_load_ps(w + 120);
122 vacc01234567p0 = _mm256_fmadd_ps(vi6x01234567, vk6x01234567, vacc01234567p0);
123 vacc89ABCDEFp0 = _mm256_fmadd_ps(vi6x89ABCDEF, vk6x89ABCDEF, vacc89ABCDEFp0);
124
125 const __m256 vi7x01234567 = _mm256_loadu_ps(i7);
126 const __m256 vi7x89ABCDEF = _mm256_loadu_ps(i7 + 8);
127 i7 += 16;
128
129 const __m256 vk7x01234567 = _mm256_load_ps(w + 128);
130 const __m256 vk7x89ABCDEF = _mm256_load_ps(w + 136);
131 vacc01234567p1 = _mm256_fmadd_ps(vi7x01234567, vk7x01234567, vacc01234567p1);
132 vacc89ABCDEFp1 = _mm256_fmadd_ps(vi7x89ABCDEF, vk7x89ABCDEF, vacc89ABCDEFp1);
133
134 const __m256 vi8x01234567 = _mm256_loadu_ps(i8);
135 const __m256 vi8x89ABCDEF = _mm256_loadu_ps(i8 + 8);
136 i8 += 16;
137
138 const __m256 vk8x01234567 = _mm256_load_ps(w + 144);
139 const __m256 vk8x89ABCDEF = _mm256_load_ps(w + 152);
140 vacc01234567p0 = _mm256_fmadd_ps(vi8x01234567, vk8x01234567, vacc01234567p0);
141 vacc89ABCDEFp0 = _mm256_fmadd_ps(vi8x89ABCDEF, vk8x89ABCDEF, vacc89ABCDEFp0);
142
143 w += 160;
144
145 // Add up all accumulators to vacc0123456789ABCDEFp0
146 vacc01234567p0 = _mm256_add_ps(vacc01234567p0, vacc01234567p1);
147 vacc89ABCDEFp0 = _mm256_add_ps(vacc89ABCDEFp0, vacc89ABCDEFp1);
148
149 __m256 vacc01234567 = _mm256_max_ps(vacc01234567p0, vmin);
150 __m256 vacc89ABCDEF = _mm256_max_ps(vacc89ABCDEFp0, vmin);
151 vacc01234567 = _mm256_min_ps(vacc01234567, vmax);
152 vacc89ABCDEF = _mm256_min_ps(vacc89ABCDEF, vmax);
153
154 _mm256_storeu_ps(output, vacc01234567);
155 _mm256_storeu_ps(output + 8, vacc89ABCDEF);
156 output += 16;
157 }
158 for (; c >= 8; c -= 8) {
159 __m256 vacc01234567p0 = _mm256_load_ps(w);
160
161 const __m256 vi0x01234567 = _mm256_loadu_ps(i0);
162 i0 += 8;
163
164 const __m256 vk0x01234567 = _mm256_load_ps(w + 16);
165 vacc01234567p0 = _mm256_fmadd_ps(vi0x01234567, vk0x01234567, vacc01234567p0);
166
167 const __m256 vi1x01234567 = _mm256_loadu_ps(i1);
168 i1 += 8;
169
170 const __m256 vk1x01234567 = _mm256_load_ps(w + 32);
171 __m256 vacc01234567p1 = _mm256_mul_ps(vi1x01234567, vk1x01234567);
172
173 const __m256 vi2x01234567 = _mm256_loadu_ps(i2);
174 i2 += 8;
175
176 const __m256 vk2x01234567 = _mm256_load_ps(w + 48);
177 vacc01234567p0 = _mm256_fmadd_ps(vi2x01234567, vk2x01234567, vacc01234567p0);
178
179 const __m256 vi3x01234567 = _mm256_loadu_ps(i3);
180 i3 += 8;
181
182 const __m256 vk3x01234567 = _mm256_load_ps(w + 64);
183 vacc01234567p1 = _mm256_fmadd_ps(vi3x01234567, vk3x01234567, vacc01234567p1);
184
185 const __m256 vi4x01234567 = _mm256_loadu_ps(i4);
186 i4 += 8;
187
188 const __m256 vk4x01234567 = _mm256_load_ps(w + 80);
189 vacc01234567p0 = _mm256_fmadd_ps(vi4x01234567, vk4x01234567, vacc01234567p0);
190
191 const __m256 vi5x01234567 = _mm256_loadu_ps(i5);
192 i5 += 8;
193
194 const __m256 vk5x01234567 = _mm256_load_ps(w + 96);
195 vacc01234567p1 = _mm256_fmadd_ps(vi5x01234567, vk5x01234567, vacc01234567p1);
196
197 const __m256 vi6x01234567 = _mm256_loadu_ps(i6);
198 i6 += 8;
199
200 const __m256 vk6x01234567 = _mm256_load_ps(w + 112);
201 vacc01234567p0 = _mm256_fmadd_ps(vi6x01234567, vk6x01234567, vacc01234567p0);
202
203 const __m256 vi7x01234567 = _mm256_loadu_ps(i7);
204 i7 += 8;
205
206 const __m256 vk7x01234567 = _mm256_load_ps(w + 128);
207 vacc01234567p1 = _mm256_fmadd_ps(vi7x01234567, vk7x01234567, vacc01234567p1);
208
209 const __m256 vi8x01234567 = _mm256_loadu_ps(i8);
210 i8 += 8;
211
212 const __m256 vk8x01234567 = _mm256_load_ps(w + 144);
213 vacc01234567p0 = _mm256_fmadd_ps(vi8x01234567, vk8x01234567, vacc01234567p0);
214
215 w += 8;
216
217 // Add up all accumulators to vacc01234567p0
218 vacc01234567p0 = _mm256_add_ps(vacc01234567p0, vacc01234567p1);
219
220 __m256 vacc01234567 = _mm256_max_ps(vacc01234567p0, vmin);
221 vacc01234567 = _mm256_min_ps(vacc01234567, vmax);
222
223 _mm256_storeu_ps(output, vacc01234567);
224 output += 8;
225 }
226 if XNN_UNLIKELY(c != 0) {
227 assert(c >= 1);
228 assert(c <= 7);
229 __m256i vmask = _mm256_loadu_si256((const __m256i*) &mask_table[7 - c]);
230
231 __m256 vacc01234567p0 = _mm256_load_ps(w);
232
233 const __m256 vi0x01234567 = _mm256_maskload_ps(i0, vmask);
234 const __m256 vk0x01234567 = _mm256_load_ps(w + 16);
235 vacc01234567p0 = _mm256_fmadd_ps(vi0x01234567, vk0x01234567, vacc01234567p0);
236
237 const __m256 vi1x01234567 = _mm256_maskload_ps(i1, vmask);
238 const __m256 vk1x01234567 = _mm256_load_ps(w + 32);
239 __m256 vacc01234567p1 = _mm256_mul_ps(vi1x01234567, vk1x01234567);
240
241 const __m256 vi2x01234567 = _mm256_maskload_ps(i2, vmask);
242 const __m256 vk2x01234567 = _mm256_load_ps(w + 48);
243 vacc01234567p0 = _mm256_fmadd_ps(vi2x01234567, vk2x01234567, vacc01234567p0);
244
245 const __m256 vi3x01234567 = _mm256_maskload_ps(i3, vmask);
246 const __m256 vk3x01234567 = _mm256_load_ps(w + 64);
247 vacc01234567p1 = _mm256_fmadd_ps(vi3x01234567, vk3x01234567, vacc01234567p1);
248
249 const __m256 vi4x01234567 = _mm256_maskload_ps(i4, vmask);
250 const __m256 vk4x01234567 = _mm256_load_ps(w + 80);
251 vacc01234567p0 = _mm256_fmadd_ps(vi4x01234567, vk4x01234567, vacc01234567p0);
252
253 const __m256 vi5x01234567 = _mm256_maskload_ps(i5, vmask);
254 const __m256 vk5x01234567 = _mm256_load_ps(w + 96);
255 vacc01234567p1 = _mm256_fmadd_ps(vi5x01234567, vk5x01234567, vacc01234567p1);
256
257 const __m256 vi6x01234567 = _mm256_maskload_ps(i6, vmask);
258 const __m256 vk6x01234567 = _mm256_load_ps(w + 112);
259 vacc01234567p0 = _mm256_fmadd_ps(vi6x01234567, vk6x01234567, vacc01234567p0);
260
261 const __m256 vi7x01234567 = _mm256_maskload_ps(i7, vmask);
262 const __m256 vk7x01234567 = _mm256_load_ps(w + 128);
263 vacc01234567p1 = _mm256_fmadd_ps(vi7x01234567, vk7x01234567, vacc01234567p1);
264
265 const __m256 vi8x01234567 = _mm256_maskload_ps(i8, vmask);
266 const __m256 vk8x01234567 = _mm256_load_ps(w + 144);
267 vacc01234567p0 = _mm256_fmadd_ps(vi8x01234567, vk8x01234567, vacc01234567p0);
268
269 // Add up all accumulators to vacc01234567p0
270 vacc01234567p0 = _mm256_add_ps(vacc01234567p0, vacc01234567p1);
271
272 __m256 vacc01234567 = _mm256_max_ps(vacc01234567p0, vmin);
273 vacc01234567 = _mm256_min_ps(vacc01234567, vmax);
274
275 // _mm256_maskstore_ps(output, vmask, vacc01234567); output += c; could be used here, but triggers msan failures (probably an msan bug).
276 __m128 vacc0123 = _mm256_castps256_ps128(vacc01234567);
277 if (c & 4) {
278 _mm_storeu_ps(output, vacc0123);
279 vacc0123 = _mm256_extractf128_ps(vacc01234567, 1);
280 output += 4;
281 }
282 if (c & 2) {
283 _mm_storel_pi((__m64*) output, vacc0123);
284 vacc0123 = _mm_movehl_ps(vacc0123, vacc0123);
285 output += 2;
286 }
287 if (c & 1) {
288 _mm_store_ss(output, vacc0123);
289 output += 1;
290 }
291 }
292
293 output = (float*) ((uintptr_t) output + output_increment);
294 } while (--output_width != 0);
295 }
296