1 // Auto-generated file. Do not edit!
2 // Template: src/f32-raddstoreexpminusmax/neon-p5.c.in
3 // Generator: tools/xngen
4 //
5 // Copyright 2020 Google LLC
6 //
7 // This source code is licensed under the BSD-style license found in the
8 // LICENSE file in the root directory of this source tree.
9
10 #include <assert.h>
11
12 #include <arm_neon.h>
13
14 #include <xnnpack/common.h>
15 #include <xnnpack/raddstoreexpminusmax.h>
16
17
xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x20(size_t elements,const float * input,float * output,float * sum,float max)18 void xnn_f32_raddstoreexpminusmax_ukernel__neonfma_p5_x20(
19 size_t elements,
20 const float* input,
21 float* output,
22 float* sum,
23 float max)
24 {
25 assert(elements % sizeof(float) == 0);
26
27 const float32x4_t vmagic_bias = vmovq_n_f32(0x1.8000FEp23f);
28 // The smallest x for which expf(x) is normalized.
29 const float32x4_t vdenorm_cutoff = vmovq_n_f32(-0x1.5D589Ep6f);
30 const float32x4_t vlog2e = vmovq_n_f32(0x1.715476p+0f);
31 const float32x4_t vminus_ln2_hi = vmovq_n_f32(-0x1.62E43p-1f);
32 const float32x4_t vminus_ln2_lo = vmovq_n_f32(0x1.05C61p-29f);
33
34 const float32x4_t vc1 = vmovq_n_f32(0x1.FFFFF6p-1f);
35 const float32x4_t vc2 = vmovq_n_f32(0x1.FFFDC6p-2f);
36 const float32x4_t vc3 = vmovq_n_f32(0x1.555A80p-3f);
37 const float32x4_t vc4 = vmovq_n_f32(0x1.573A1Ap-5f);
38 const float32x4_t vc5 = vmovq_n_f32(0x1.0F9F9Cp-7f);
39
40 const float32x4_t vi_max = vdupq_n_f32(max);
41
42 float32x4_t vacc0 = vmovq_n_f32(0.0f);
43 for (; elements >= 20 * sizeof(float); elements -= 20 * sizeof(float)) {
44 // Load 20 (5x4) inputs at a time.
45 const float32x4_t vi0123 = vld1q_f32(input); input += 4;
46 const float32x4_t vi4567 = vld1q_f32(input); input += 4;
47 const float32x4_t vi89AB = vld1q_f32(input); input += 4;
48 const float32x4_t viCDEF = vld1q_f32(input); input += 4;
49 const float32x4_t viGHIJ = vld1q_f32(input); input += 4;
50
51 // Subtract maximum input x := i - i_max. This implies x <= 0.
52 const float32x4_t vx0123 = vsubq_f32(vi0123, vi_max);
53 const float32x4_t vx4567 = vsubq_f32(vi4567, vi_max);
54 const float32x4_t vx89AB = vsubq_f32(vi89AB, vi_max);
55 const float32x4_t vxCDEF = vsubq_f32(viCDEF, vi_max);
56 const float32x4_t vxGHIJ = vsubq_f32(viGHIJ, vi_max);
57
58 // Compute reduced argument n := round(x / log(2)).
59 // We do it by adding a large number (magic bias), which cause rounding of result to an integer, then subtracing the
60 // large number back. The first addition is combined with multiplication by log2e into a single FMA instruction.
61 // The trick with adding large number is valid only within certain bounds (|x| <= 2**22), but thats ok, because
62 // inputs outside of [-87.336540, 0.0] underflow expf(x) anyway. We fixup the result for such inputs at the very end
63 // of the algorithm.
64 float32x4_t vn0123 = vfmaq_f32(vmagic_bias, vx0123, vlog2e);
65 float32x4_t vn4567 = vfmaq_f32(vmagic_bias, vx4567, vlog2e);
66 float32x4_t vn89AB = vfmaq_f32(vmagic_bias, vx89AB, vlog2e);
67 float32x4_t vnCDEF = vfmaq_f32(vmagic_bias, vxCDEF, vlog2e);
68 float32x4_t vnGHIJ = vfmaq_f32(vmagic_bias, vxGHIJ, vlog2e);
69
70 // Create a floating-point number s (scale) such that s == 2**n for inputs which don't cause underflow, i.e.
71 // -87.33642 <= x <= 0.0, and -126 <= n <= 0 accordingly.
72 const float32x4_t vs0123 = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn0123), 23));
73 const float32x4_t vs4567 = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn4567), 23));
74 const float32x4_t vs89AB = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn89AB), 23));
75 const float32x4_t vsCDEF = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vnCDEF), 23));
76 const float32x4_t vsGHIJ = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vnGHIJ), 23));
77
78 // Subtract the large number back to get final n := round(x / log(2)).
79 vn0123 = vsubq_f32(vn0123, vmagic_bias);
80 vn4567 = vsubq_f32(vn4567, vmagic_bias);
81 vn89AB = vsubq_f32(vn89AB, vmagic_bias);
82 vnCDEF = vsubq_f32(vnCDEF, vmagic_bias);
83 vnGHIJ = vsubq_f32(vnGHIJ, vmagic_bias);
84
85 // Compute reduced argument t := z - n * log(2).
86 // Use Cody-Waite range reduction method (note two constants to represent log(2)) to improve accuracy.
87 float32x4_t vt0123 = vfmaq_f32(vx0123, vn0123, vminus_ln2_hi);
88 float32x4_t vt4567 = vfmaq_f32(vx4567, vn4567, vminus_ln2_hi);
89 float32x4_t vt89AB = vfmaq_f32(vx89AB, vn89AB, vminus_ln2_hi);
90 float32x4_t vtCDEF = vfmaq_f32(vxCDEF, vnCDEF, vminus_ln2_hi);
91 float32x4_t vtGHIJ = vfmaq_f32(vxGHIJ, vnGHIJ, vminus_ln2_hi);
92
93 vt0123 = vfmaq_f32(vt0123, vn0123, vminus_ln2_lo);
94 vt4567 = vfmaq_f32(vt4567, vn4567, vminus_ln2_lo);
95 vt89AB = vfmaq_f32(vt89AB, vn89AB, vminus_ln2_lo);
96 vtCDEF = vfmaq_f32(vtCDEF, vnCDEF, vminus_ln2_lo);
97 vtGHIJ = vfmaq_f32(vtGHIJ, vnGHIJ, vminus_ln2_lo);
98
99 // Compute degree-5 polynomial approxiatmion for exp(t) on [-log(2)/2, log(2)/2].
100 float32x4_t vp0123 = vfmaq_f32(vc4, vc5, vt0123);
101 float32x4_t vp4567 = vfmaq_f32(vc4, vc5, vt4567);
102 float32x4_t vp89AB = vfmaq_f32(vc4, vc5, vt89AB);
103 float32x4_t vpCDEF = vfmaq_f32(vc4, vc5, vtCDEF);
104 float32x4_t vpGHIJ = vfmaq_f32(vc4, vc5, vtGHIJ);
105
106 vp0123 = vfmaq_f32(vc3, vp0123, vt0123);
107 vp4567 = vfmaq_f32(vc3, vp4567, vt4567);
108 vp89AB = vfmaq_f32(vc3, vp89AB, vt89AB);
109 vpCDEF = vfmaq_f32(vc3, vpCDEF, vtCDEF);
110 vpGHIJ = vfmaq_f32(vc3, vpGHIJ, vtGHIJ);
111
112 vp0123 = vfmaq_f32(vc2, vp0123, vt0123);
113 vp4567 = vfmaq_f32(vc2, vp4567, vt4567);
114 vp89AB = vfmaq_f32(vc2, vp89AB, vt89AB);
115 vpCDEF = vfmaq_f32(vc2, vpCDEF, vtCDEF);
116 vpGHIJ = vfmaq_f32(vc2, vpGHIJ, vtGHIJ);
117
118 vp0123 = vfmaq_f32(vc1, vp0123, vt0123);
119 vp4567 = vfmaq_f32(vc1, vp4567, vt4567);
120 vp89AB = vfmaq_f32(vc1, vp89AB, vt89AB);
121 vpCDEF = vfmaq_f32(vc1, vpCDEF, vtCDEF);
122 vpGHIJ = vfmaq_f32(vc1, vpGHIJ, vtGHIJ);
123
124 // Reconstruct the final f value:
125 // f = s * (1 + t * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5)))))
126 // = s + (t * s) * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5))))
127 // = s + (t * s) * p
128 vt0123 = vmulq_f32(vt0123, vs0123);
129 vt4567 = vmulq_f32(vt4567, vs4567);
130 vt89AB = vmulq_f32(vt89AB, vs89AB);
131 vtCDEF = vmulq_f32(vtCDEF, vsCDEF);
132 vtGHIJ = vmulq_f32(vtGHIJ, vsGHIJ);
133
134 float32x4_t vf0123 = vfmaq_f32(vs0123, vp0123, vt0123);
135 float32x4_t vf4567 = vfmaq_f32(vs4567, vp4567, vt4567);
136 float32x4_t vf89AB = vfmaq_f32(vs89AB, vp89AB, vt89AB);
137 float32x4_t vfCDEF = vfmaq_f32(vsCDEF, vpCDEF, vtCDEF);
138 float32x4_t vfGHIJ = vfmaq_f32(vsGHIJ, vpGHIJ, vtGHIJ);
139
140 // For inputs below denormal cutoff, replace output with +0.0f.
141 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
142 vf0123 = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf0123), vcltq_f32(vx0123, vdenorm_cutoff)));
143 vf4567 = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf4567), vcltq_f32(vx4567, vdenorm_cutoff)));
144 vf89AB = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf89AB), vcltq_f32(vx89AB, vdenorm_cutoff)));
145 vfCDEF = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vfCDEF), vcltq_f32(vxCDEF, vdenorm_cutoff)));
146 vfGHIJ = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vfGHIJ), vcltq_f32(vxGHIJ, vdenorm_cutoff)));
147
148 // Store 20 (5x4) outputs at a time.
149 vst1q_f32(output, vf0123); output += 4;
150 vst1q_f32(output, vf4567); output += 4;
151 vst1q_f32(output, vf89AB); output += 4;
152 vst1q_f32(output, vfCDEF); output += 4;
153 vst1q_f32(output, vfGHIJ); output += 4;
154
155 // Accumulate computed exponents.
156 vacc0 = vaddq_f32(vacc0, vf0123);
157 vacc0 = vaddq_f32(vacc0, vf4567);
158 vacc0 = vaddq_f32(vacc0, vf89AB);
159 vacc0 = vaddq_f32(vacc0, vfCDEF);
160 vacc0 = vaddq_f32(vacc0, vfGHIJ);
161 }
162
163 float32x4_t vacc = vacc0;
164 for (; elements >= 4 * sizeof(float); elements -= 4 * sizeof(float)) {
165 // Load 4 inputs at a time.
166 const float32x4_t vi = vld1q_f32(input); input += 4;
167
168 // Subtract maximum input x := i - i_max. This implies x <= 0.
169 const float32x4_t vx = vsubq_f32(vi, vi_max);
170
171 // Compute reduced argument n := round(x / log(2)).
172 // We do it by adding a large number (magic bias), which cause rounding of result to an integer, then subtracing the
173 // large number back. The first addition is combined with multiplication by log2e into a single FMA instruction.
174 // The trick with adding large number is valid only within certain bounds (|x| <= 2**22), but thats ok, because
175 // inputs outside of [-87.336540, 0.0] underflow expf(x) anyway. We fixup the result for such inputs at the very end
176 // of the algorithm.
177 float32x4_t vn = vfmaq_f32(vmagic_bias, vx, vlog2e);
178
179 // Create a floating-point number s (scale) such that s == 2**n for inputs which don't cause underflow, i.e.
180 // -87.33642 <= x <= 0.0, and -126 <= n <= 0 accordingly.
181 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
182
183 // Subtract the large number back to get final n := round(x / log(2)).
184 vn = vsubq_f32(vn, vmagic_bias);
185
186 // Compute reduced argument t := z - n * log(2).
187 // Use Cody-Waite range reduction method (note two constants to represent log(2)) to improve accuracy.
188 float32x4_t vt = vfmaq_f32(vx, vn, vminus_ln2_hi);
189 vt = vfmaq_f32(vt, vn, vminus_ln2_lo);
190
191 // Compute degree-5 polynomial approxiatmion for exp(t) on [-log(2)/2, log(2)/2].
192 float32x4_t vp = vfmaq_f32(vc4, vc5, vt);
193 vp = vfmaq_f32(vc3, vp, vt);
194 vp = vfmaq_f32(vc2, vp, vt);
195 vp = vfmaq_f32(vc1, vp, vt);
196
197 // Reconstruct the final f value:
198 // f = s * (1 + t * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5)))))
199 // = s + (t * s) * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5))))
200 // = s + (t * s) * p
201 vt = vmulq_f32(vt, vs);
202 float32x4_t vf = vfmaq_f32(vs, vp, vt);
203
204 // For inputs below denormal cutoff, replace output with +0.0f.
205 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
206 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
207
208 // Store 4 outputs at a time.
209 vst1q_f32(output, vf); output += 4;
210
211 // Accumulate computed exponents.
212 vacc = vaddq_f32(vacc, vf);
213 }
214 #if XNN_ARCH_ARM64
215 float vacc_lo = vaddvq_f32(vacc);
216 #else
217 float32x2_t vacc_lo = vadd_f32(vget_high_f32(vacc), vget_low_f32(vacc));
218 #endif
219 if (elements != 0) {
220 assert(elements >= 1 * sizeof(float));
221 assert(elements <= 3 * sizeof(float));
222 // Load 4 inputs at a time.
223 const float32x4_t vi = vld1q_f32(input); input += 4;
224
225 // Subtract maximum input x := i - i_max. This implies x <= 0.
226 const float32x4_t vx = vsubq_f32(vi, vi_max);
227
228 // Compute reduced argument n := round(x / log(2)).
229 // We do it by adding a large number (magic bias), which cause rounding of result to an integer, then subtracing the
230 // large number back. The first addition is combined with multiplication by log2e into a single FMA instruction.
231 // The trick with adding large number is valid only within certain bounds (|x| <= 2**22), but thats ok, because
232 // inputs outside of [-87.336540, 0.0] underflow expf(x) anyway. We fixup the result for such inputs at the very end
233 // of the algorithm.
234 float32x4_t vn = vfmaq_f32(vmagic_bias, vx, vlog2e);
235
236 // Create a floating-point number s (scale) such that s == 2**n for inputs which don't cause underflow, i.e.
237 // -87.33642 <= x <= 0.0, and -126 <= n <= 0 accordingly.
238 const float32x4_t vs = vreinterpretq_f32_s32(vshlq_n_s32(vreinterpretq_s32_f32(vn), 23));
239
240 // Subtract the large number back to get final n := round(x / log(2)).
241 vn = vsubq_f32(vn, vmagic_bias);
242
243 // Compute reduced argument t := z - n * log(2).
244 // Use Cody-Waite range reduction method (note two constants to represent log(2)) to improve accuracy.
245 float32x4_t vt = vfmaq_f32(vx, vn, vminus_ln2_hi);
246 vt = vfmaq_f32(vt, vn, vminus_ln2_lo);
247
248 // Compute degree-5 polynomial approxiatmion for exp(t) on [-log(2)/2, log(2)/2].
249 float32x4_t vp = vfmaq_f32(vc4, vc5, vt);
250 vp = vfmaq_f32(vc3, vp, vt);
251 vp = vfmaq_f32(vc2, vp, vt);
252 vp = vfmaq_f32(vc1, vp, vt);
253
254 // Reconstruct the final f value:
255 // f = s * (1 + t * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5)))))
256 // = s + (t * s) * (c1 + t * (c2 + t * (c3 + t * (c4 + t * c5))))
257 // = s + (t * s) * p
258 vt = vmulq_f32(vt, vs);
259 float32x4_t vf = vfmaq_f32(vs, vp, vt);
260
261 // For inputs below denormal cutoff, replace output with +0.0f.
262 // Note that for NaN inputs, comparison result is false, and outputs are left unchanged.
263 vf = vreinterpretq_f32_u32(vbicq_u32(vreinterpretq_u32_f32(vf), vcltq_f32(vx, vdenorm_cutoff)));
264
265 float32x2_t vf_lo = vget_low_f32(vf);
266 if (elements & (2 * sizeof(float))) {
267 // Store 2 outputs at a time.
268 vst1_f32(output, vf_lo); output += 2;
269
270 // Accumulate 2 computed exponents.
271 #if XNN_ARCH_ARM64
272 vacc_lo += vaddv_f32(vf_lo);
273 #else
274 vacc_lo = vadd_f32(vacc_lo, vf_lo);
275 #endif
276
277 vf_lo = vget_high_f32(vf);
278 }
279 if (elements & (1 * sizeof(float))) {
280 // Store 1 output at a time.
281 vst1_lane_f32(output, vf_lo, 0);
282
283 // Accumulate 1 computed exponent.
284 #if XNN_ARCH_ARM64
285 vacc_lo += vget_lane_f32(vf_lo, 0);
286 #else
287 vacc_lo = vadd_f32(vacc_lo, vreinterpret_f32_u64(vshl_n_u64(vreinterpret_u64_f32(vf_lo), 32)));
288 #endif
289 }
290 }
291 // Reduce 4 elements in the SIMD register
292 #if XNN_ARCH_ARM64
293 *sum = vacc_lo;
294 #else
295 vst1_lane_f32(sum, vpadd_f32(vacc_lo, vacc_lo), 0);
296 #endif
297 }
298