1/* 2 * strcmp for ARMv6-M (optimized for performance, not size) 3 * 4 * Copyright (c) 2014-2019, Arm Limited. 5 * SPDX-License-Identifier: MIT 6 */ 7 8 .thumb_func 9 .syntax unified 10 .arch armv6-m 11 12 .macro DoSub n, label 13 subs r0, r0, r1 14#ifdef __ARM_BIG_ENDIAN 15 lsrs r1, r4, \n 16#else 17 lsls r1, r4, \n 18#endif 19 orrs r1, r0 20 bne \label 21 .endm 22 23 .macro Byte_Test n, label 24 lsrs r0, r2, \n 25 lsrs r1, r3, \n 26 DoSub \n, \label 27 .endm 28 29ENTRY_ALIGN (__strcmp_armv6m, 4) 30 mov r2, r0 31 push {r4, r5, r6, lr} 32 orrs r2, r1 33 lsls r2, r2, #30 34 bne 6f 35 ldr r5, =0x01010101 36 lsls r6, r5, #7 371: 38 ldmia r0!, {r2} 39 ldmia r1!, {r3} 40 subs r4, r2, r5 41 bics r4, r2 42 ands r4, r6 43 beq 3f 44 45#ifdef __ARM_BIG_ENDIAN 46 Byte_Test #24, 4f 47 Byte_Test #16, 4f 48 Byte_Test #8, 4f 49 50 b 7f 513: 52 cmp r2, r3 53 beq 1b 54 cmp r2, r3 55#else 56 uxtb r0, r2 57 uxtb r1, r3 58 DoSub #24, 2f 59 60 uxth r0, r2 61 uxth r1, r3 62 DoSub #16, 2f 63 64 lsls r0, r2, #8 65 lsls r1, r3, #8 66 lsrs r0, r0, #8 67 lsrs r1, r1, #8 68 DoSub #8, 2f 69 70 lsrs r0, r2, #24 71 lsrs r1, r3, #24 72 subs r0, r0, r1 732: 74 pop {r4, r5, r6, pc} 75 763: 77 cmp r2, r3 78 beq 1b 79 rev r0, r2 80 rev r1, r3 81 cmp r0, r1 82#endif 83 84 bls 5f 85 movs r0, #1 864: 87 pop {r4, r5, r6, pc} 885: 89 movs r0, #0 90 mvns r0, r0 91 pop {r4, r5, r6, pc} 926: 93 ldrb r2, [r0, #0] 94 ldrb r3, [r1, #0] 95 adds r0, #1 96 adds r1, #1 97 cmp r2, #0 98 beq 7f 99 cmp r2, r3 100 bne 7f 101 ldrb r2, [r0, #0] 102 ldrb r3, [r1, #0] 103 adds r0, #1 104 adds r1, #1 105 cmp r2, #0 106 beq 7f 107 cmp r2, r3 108 beq 6b 1097: 110 subs r0, r2, r3 111 pop {r4, r5, r6, pc} 112 113END (__strcmp_armv6m) 114