1/* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <lib/xlat_tables/xlat_tables_defs.h> 10 11OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 12OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 13ENTRY(bl2u_entrypoint) 14 15MEMORY { 16 RAM (rwx): ORIGIN = BL2U_BASE, LENGTH = BL2U_LIMIT - BL2U_BASE 17} 18 19 20SECTIONS 21{ 22 . = BL2U_BASE; 23 ASSERT(. == ALIGN(PAGE_SIZE), 24 "BL2U_BASE address is not aligned on a page boundary.") 25 26#if SEPARATE_CODE_AND_RODATA 27 .text . : { 28 __TEXT_START__ = .; 29 *bl2u_entrypoint.o(.text*) 30 *(SORT_BY_ALIGNMENT(.text*)) 31 *(.vectors) 32 . = ALIGN(PAGE_SIZE); 33 __TEXT_END__ = .; 34 } >RAM 35 36 /* .ARM.extab and .ARM.exidx are only added because Clang need them */ 37 .ARM.extab . : { 38 *(.ARM.extab* .gnu.linkonce.armextab.*) 39 } >RAM 40 41 .ARM.exidx . : { 42 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 43 } >RAM 44 45 .rodata . : { 46 __RODATA_START__ = .; 47 *(SORT_BY_ALIGNMENT(.rodata*)) 48 . = ALIGN(PAGE_SIZE); 49 __RODATA_END__ = .; 50 } >RAM 51#else 52 ro . : { 53 __RO_START__ = .; 54 *bl2u_entrypoint.o(.text*) 55 *(SORT_BY_ALIGNMENT(.text*)) 56 *(SORT_BY_ALIGNMENT(.rodata*)) 57 58 *(.vectors) 59 __RO_END_UNALIGNED__ = .; 60 /* 61 * Memory page(s) mapped to this section will be marked as 62 * read-only, executable. No RW data from the next section must 63 * creep in. Ensure the rest of the current memory page is unused. 64 */ 65 . = ALIGN(PAGE_SIZE); 66 __RO_END__ = .; 67 } >RAM 68#endif 69 70 /* 71 * Define a linker symbol to mark start of the RW memory area for this 72 * image. 73 */ 74 __RW_START__ = . ; 75 76 /* 77 * .data must be placed at a lower address than the stacks if the stack 78 * protector is enabled. Alternatively, the .data.stack_protector_canary 79 * section can be placed independently of the main .data section. 80 */ 81 .data . : { 82 __DATA_START__ = .; 83 *(SORT_BY_ALIGNMENT(.data*)) 84 __DATA_END__ = .; 85 } >RAM 86 87 stacks (NOLOAD) : { 88 __STACKS_START__ = .; 89 *(tzfw_normal_stacks) 90 __STACKS_END__ = .; 91 } >RAM 92 93 /* 94 * The .bss section gets initialised to 0 at runtime. 95 * Its base address should be 16-byte aligned for better performance of the 96 * zero-initialization code. 97 */ 98 .bss : ALIGN(16) { 99 __BSS_START__ = .; 100 *(SORT_BY_ALIGNMENT(.bss*)) 101 *(COMMON) 102 __BSS_END__ = .; 103 } >RAM 104 105 /* 106 * The xlat_table section is for full, aligned page tables (4K). 107 * Removing them from .bss avoids forcing 4K alignment on 108 * the .bss section. The tables are initialized to zero by the translation 109 * tables library. 110 */ 111 xlat_table (NOLOAD) : { 112 *(xlat_table) 113 } >RAM 114 115#if USE_COHERENT_MEM 116 /* 117 * The base address of the coherent memory section must be page-aligned (4K) 118 * to guarantee that the coherent data are stored on their own pages and 119 * are not mixed with normal data. This is required to set up the correct 120 * memory attributes for the coherent data page tables. 121 */ 122 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 123 __COHERENT_RAM_START__ = .; 124 *(tzfw_coherent_mem) 125 __COHERENT_RAM_END_UNALIGNED__ = .; 126 /* 127 * Memory page(s) mapped to this section will be marked 128 * as device memory. No other unexpected data must creep in. 129 * Ensure the rest of the current memory page is unused. 130 */ 131 . = ALIGN(PAGE_SIZE); 132 __COHERENT_RAM_END__ = .; 133 } >RAM 134#endif 135 136 /* 137 * Define a linker symbol to mark end of the RW memory area for this 138 * image. 139 */ 140 __RW_END__ = .; 141 __BL2U_END__ = .; 142 143 __BSS_SIZE__ = SIZEOF(.bss); 144 145 ASSERT(. <= BL2U_LIMIT, "BL2U image has exceeded its limit.") 146} 147