1/* 2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <lib/xlat_tables/xlat_tables_defs.h> 10 11OUTPUT_FORMAT(elf32-littlearm) 12OUTPUT_ARCH(arm) 13ENTRY(sp_min_vector_table) 14 15MEMORY { 16 RAM (rwx): ORIGIN = BL32_BASE, LENGTH = BL32_LIMIT - BL32_BASE 17} 18 19#ifdef PLAT_SP_MIN_EXTRA_LD_SCRIPT 20#include <plat_sp_min.ld.S> 21#endif 22 23SECTIONS 24{ 25 . = BL32_BASE; 26 ASSERT(. == ALIGN(PAGE_SIZE), 27 "BL32_BASE address is not aligned on a page boundary.") 28 29#if SEPARATE_CODE_AND_RODATA 30 .text . : { 31 __TEXT_START__ = .; 32 *entrypoint.o(.text*) 33 *(.text*) 34 *(.vectors) 35 . = ALIGN(PAGE_SIZE); 36 __TEXT_END__ = .; 37 } >RAM 38 39 /* .ARM.extab and .ARM.exidx are only added because Clang need them */ 40 .ARM.extab . : { 41 *(.ARM.extab* .gnu.linkonce.armextab.*) 42 } >RAM 43 44 .ARM.exidx . : { 45 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 46 } >RAM 47 48 .rodata . : { 49 __RODATA_START__ = .; 50 *(.rodata*) 51 52 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 53 . = ALIGN(4); 54 __RT_SVC_DESCS_START__ = .; 55 KEEP(*(rt_svc_descs)) 56 __RT_SVC_DESCS_END__ = .; 57 58#if ENABLE_PMF 59 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 60 . = ALIGN(4); 61 __PMF_SVC_DESCS_START__ = .; 62 KEEP(*(pmf_svc_descs)) 63 __PMF_SVC_DESCS_END__ = .; 64#endif /* ENABLE_PMF */ 65 66 /* 67 * Ensure 4-byte alignment for cpu_ops so that its fields are also 68 * aligned. Also ensure cpu_ops inclusion. 69 */ 70 . = ALIGN(4); 71 __CPU_OPS_START__ = .; 72 KEEP(*(cpu_ops)) 73 __CPU_OPS_END__ = .; 74 75 /* Place pubsub sections for events */ 76 . = ALIGN(8); 77#include <lib/el3_runtime/pubsub_events.h> 78 79 . = ALIGN(PAGE_SIZE); 80 __RODATA_END__ = .; 81 } >RAM 82#else 83 ro . : { 84 __RO_START__ = .; 85 *entrypoint.o(.text*) 86 *(.text*) 87 *(.rodata*) 88 89 /* Ensure 4-byte alignment for descriptors and ensure inclusion */ 90 . = ALIGN(4); 91 __RT_SVC_DESCS_START__ = .; 92 KEEP(*(rt_svc_descs)) 93 __RT_SVC_DESCS_END__ = .; 94 95 /* 96 * Ensure 4-byte alignment for cpu_ops so that its fields are also 97 * aligned. Also ensure cpu_ops inclusion. 98 */ 99 . = ALIGN(4); 100 __CPU_OPS_START__ = .; 101 KEEP(*(cpu_ops)) 102 __CPU_OPS_END__ = .; 103 104 /* Place pubsub sections for events */ 105 . = ALIGN(8); 106#include <lib/el3_runtime/pubsub_events.h> 107 108 *(.vectors) 109 __RO_END_UNALIGNED__ = .; 110 111 /* 112 * Memory page(s) mapped to this section will be marked as 113 * read-only, executable. No RW data from the next section must 114 * creep in. Ensure the rest of the current memory block is unused. 115 */ 116 . = ALIGN(PAGE_SIZE); 117 __RO_END__ = .; 118 } >RAM 119#endif 120 121 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 122 "cpu_ops not defined for this platform.") 123 /* 124 * Define a linker symbol to mark start of the RW memory area for this 125 * image. 126 */ 127 __RW_START__ = . ; 128 129 .data . : { 130 __DATA_START__ = .; 131 *(.data*) 132 __DATA_END__ = .; 133 } >RAM 134 135#ifdef BL32_PROGBITS_LIMIT 136 ASSERT(. <= BL32_PROGBITS_LIMIT, "BL32 progbits has exceeded its limit.") 137#endif 138 139 stacks (NOLOAD) : { 140 __STACKS_START__ = .; 141 *(tzfw_normal_stacks) 142 __STACKS_END__ = .; 143 } >RAM 144 145 /* 146 * The .bss section gets initialised to 0 at runtime. 147 * Its base address should be 8-byte aligned for better performance of the 148 * zero-initialization code. 149 */ 150 .bss (NOLOAD) : ALIGN(8) { 151 __BSS_START__ = .; 152 *(.bss*) 153 *(COMMON) 154#if !USE_COHERENT_MEM 155 /* 156 * Bakery locks are stored in normal .bss memory 157 * 158 * Each lock's data is spread across multiple cache lines, one per CPU, 159 * but multiple locks can share the same cache line. 160 * The compiler will allocate enough memory for one CPU's bakery locks, 161 * the remaining cache lines are allocated by the linker script 162 */ 163 . = ALIGN(CACHE_WRITEBACK_GRANULE); 164 __BAKERY_LOCK_START__ = .; 165 __PERCPU_BAKERY_LOCK_START__ = .; 166 *(bakery_lock) 167 . = ALIGN(CACHE_WRITEBACK_GRANULE); 168 __PERCPU_BAKERY_LOCK_END__ = .; 169 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__); 170 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 171 __BAKERY_LOCK_END__ = .; 172#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 173 ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, 174 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); 175#endif 176#endif 177 178#if ENABLE_PMF 179 /* 180 * Time-stamps are stored in normal .bss memory 181 * 182 * The compiler will allocate enough memory for one CPU's time-stamps, 183 * the remaining memory for other CPUs is allocated by the 184 * linker script 185 */ 186 . = ALIGN(CACHE_WRITEBACK_GRANULE); 187 __PMF_TIMESTAMP_START__ = .; 188 KEEP(*(pmf_timestamp_array)) 189 . = ALIGN(CACHE_WRITEBACK_GRANULE); 190 __PMF_PERCPU_TIMESTAMP_END__ = .; 191 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); 192 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 193 __PMF_TIMESTAMP_END__ = .; 194#endif /* ENABLE_PMF */ 195 196 __BSS_END__ = .; 197 } >RAM 198 199 /* 200 * The xlat_table section is for full, aligned page tables (4K). 201 * Removing them from .bss avoids forcing 4K alignment on 202 * the .bss section. The tables are initialized to zero by the translation 203 * tables library. 204 */ 205 xlat_table (NOLOAD) : { 206 *(xlat_table) 207 } >RAM 208 209 __BSS_SIZE__ = SIZEOF(.bss); 210 211#if USE_COHERENT_MEM 212 /* 213 * The base address of the coherent memory section must be page-aligned (4K) 214 * to guarantee that the coherent data are stored on their own pages and 215 * are not mixed with normal data. This is required to set up the correct 216 * memory attributes for the coherent data page tables. 217 */ 218 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 219 __COHERENT_RAM_START__ = .; 220 /* 221 * Bakery locks are stored in coherent memory 222 * 223 * Each lock's data is contiguous and fully allocated by the compiler 224 */ 225 *(bakery_lock) 226 *(tzfw_coherent_mem) 227 __COHERENT_RAM_END_UNALIGNED__ = .; 228 /* 229 * Memory page(s) mapped to this section will be marked 230 * as device memory. No other unexpected data must creep in. 231 * Ensure the rest of the current memory page is unused. 232 */ 233 . = ALIGN(PAGE_SIZE); 234 __COHERENT_RAM_END__ = .; 235 } >RAM 236 237 __COHERENT_RAM_UNALIGNED_SIZE__ = 238 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 239#endif 240 241 /* 242 * Define a linker symbol to mark end of the RW memory area for this 243 * image. 244 */ 245 __RW_END__ = .; 246 247 __BL32_END__ = .; 248} 249