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1/*
2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <lib/xlat_tables/xlat_tables_defs.h>
8#include <platform_def.h>
9
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(tsp_entrypoint)
13
14
15MEMORY {
16    RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE
17}
18
19
20SECTIONS
21{
22    . = BL32_BASE;
23    ASSERT(. == ALIGN(PAGE_SIZE),
24           "BL32_BASE address is not aligned on a page boundary.")
25
26#if SEPARATE_CODE_AND_RODATA
27    .text . : {
28        __TEXT_START__ = .;
29        *tsp_entrypoint.o(.text*)
30        *(.text*)
31        *(.vectors)
32        . = ALIGN(PAGE_SIZE);
33        __TEXT_END__ = .;
34    } >RAM
35
36    .rodata . : {
37        __RODATA_START__ = .;
38        *(.rodata*)
39
40        /*
41         * Keep the .got section in the RO section as it is patched
42         * prior to enabling the MMU and having the .got in RO is better for
43         * security. GOT is a table of addresses so ensure 8-byte alignment.
44         */
45        . = ALIGN(8);
46        __GOT_START__ = .;
47        *(.got)
48        __GOT_END__ = .;
49
50        . = ALIGN(PAGE_SIZE);
51        __RODATA_END__ = .;
52    } >RAM
53#else
54    ro . : {
55        __RO_START__ = .;
56        *tsp_entrypoint.o(.text*)
57        *(.text*)
58        *(.rodata*)
59
60        /*
61         * Keep the .got section in the RO section as it is patched
62         * prior to enabling the MMU and having the .got in RO is better for
63         * security. GOT is a table of addresses so ensure 8-byte alignment.
64         */
65        . = ALIGN(8);
66        __GOT_START__ = .;
67        *(.got)
68        __GOT_END__ = .;
69
70        *(.vectors)
71
72        __RO_END_UNALIGNED__ = .;
73        /*
74         * Memory page(s) mapped to this section will be marked as
75         * read-only, executable.  No RW data from the next section must
76         * creep in.  Ensure the rest of the current memory page is unused.
77         */
78        . = ALIGN(PAGE_SIZE);
79        __RO_END__ = .;
80    } >RAM
81#endif
82
83    /*
84     * Define a linker symbol to mark start of the RW memory area for this
85     * image.
86     */
87    __RW_START__ = . ;
88
89    .data . : {
90        __DATA_START__ = .;
91        *(.data*)
92        __DATA_END__ = .;
93    } >RAM
94
95    /*
96     * .rela.dyn needs to come after .data for the read-elf utility to parse
97     * this section correctly. Ensure 8-byte alignment so that the fields of
98     * RELA data structure are aligned.
99     */
100    . = ALIGN(8);
101    __RELA_START__ = .;
102    .rela.dyn . : {
103    } >RAM
104    __RELA_END__ = .;
105
106#ifdef TSP_PROGBITS_LIMIT
107    ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.")
108#endif
109
110    stacks (NOLOAD) : {
111        __STACKS_START__ = .;
112        *(tzfw_normal_stacks)
113        __STACKS_END__ = .;
114    } >RAM
115
116    /*
117     * The .bss section gets initialised to 0 at runtime.
118     * Its base address should be 16-byte aligned for better performance of the
119     * zero-initialization code.
120     */
121    .bss : ALIGN(16) {
122        __BSS_START__ = .;
123        *(SORT_BY_ALIGNMENT(.bss*))
124        *(COMMON)
125        __BSS_END__ = .;
126    } >RAM
127
128    /*
129     * The xlat_table section is for full, aligned page tables (4K).
130     * Removing them from .bss avoids forcing 4K alignment on
131     * the .bss section. The tables are initialized to zero by the translation
132     * tables library.
133     */
134    xlat_table (NOLOAD) : {
135        *(xlat_table)
136    } >RAM
137
138#if USE_COHERENT_MEM
139    /*
140     * The base address of the coherent memory section must be page-aligned (4K)
141     * to guarantee that the coherent data are stored on their own pages and
142     * are not mixed with normal data.  This is required to set up the correct
143     * memory attributes for the coherent data page tables.
144     */
145    coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
146        __COHERENT_RAM_START__ = .;
147        *(tzfw_coherent_mem)
148        __COHERENT_RAM_END_UNALIGNED__ = .;
149        /*
150         * Memory page(s) mapped to this section will be marked
151         * as device memory.  No other unexpected data must creep in.
152         * Ensure the rest of the current memory page is unused.
153         */
154        . = ALIGN(PAGE_SIZE);
155        __COHERENT_RAM_END__ = .;
156    } >RAM
157#endif
158
159    /*
160     * Define a linker symbol to mark the end of the RW memory area for this
161     * image.
162     */
163    __RW_END__ = .;
164    __BL32_END__ = .;
165
166    /DISCARD/ : {
167        *(.dynsym .dynstr .hash .gnu.hash)
168    }
169
170    __BSS_SIZE__ = SIZEOF(.bss);
171#if USE_COHERENT_MEM
172    __COHERENT_RAM_UNALIGNED_SIZE__ =
173        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
174#endif
175
176    ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.")
177}
178