1 /*
2 * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <common/debug.h>
8 #include <lib/mmio.h>
9
10 #include "emmc_config.h"
11 #include "emmc_hal.h"
12 #include "emmc_std.h"
13 #include "emmc_registers.h"
14 #include "emmc_def.h"
15 #include "micro_delay.h"
16 #include "rcar_def.h"
17
18 static EMMC_ERROR_CODE emmc_clock_ctrl(uint8_t mode);
19 static EMMC_ERROR_CODE emmc_card_init(void);
20 static EMMC_ERROR_CODE emmc_high_speed(void);
21 static EMMC_ERROR_CODE emmc_bus_width(uint32_t width);
22 static uint32_t emmc_set_timeout_register_value(uint32_t freq);
23 static void set_sd_clk(uint32_t clkDiv);
24 static uint32_t emmc_calc_tran_speed(uint32_t *freq);
25 static void emmc_get_partition_access(void);
26 static void emmc_set_bootpartition(void);
27
emmc_set_bootpartition(void)28 static void emmc_set_bootpartition(void)
29 {
30 uint32_t reg;
31
32 reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
33 if (reg == PRR_PRODUCT_M3_CUT10) {
34 mmc_drv_obj.boot_partition_en =
35 (EMMC_PARTITION_ID) ((mmc_drv_obj.ext_csd_data[179] &
36 EMMC_BOOT_PARTITION_EN_MASK) >>
37 EMMC_BOOT_PARTITION_EN_SHIFT);
38 } else if ((reg == PRR_PRODUCT_H3_CUT20)
39 || (reg == PRR_PRODUCT_M3_CUT11)) {
40 mmc_drv_obj.boot_partition_en = mmc_drv_obj.partition_access;
41 } else {
42 if ((mmio_read_32(MFISBTSTSR) & MFISBTSTSR_BOOT_PARTITION) !=
43 0U) {
44 mmc_drv_obj.boot_partition_en = PARTITION_ID_BOOT_2;
45 } else {
46 mmc_drv_obj.boot_partition_en = PARTITION_ID_BOOT_1;
47 }
48 }
49 }
50
emmc_card_init(void)51 static EMMC_ERROR_CODE emmc_card_init(void)
52 {
53 int32_t retry;
54 uint32_t freq = MMC_400KHZ; /* 390KHz */
55 EMMC_ERROR_CODE result;
56 uint32_t resultCalc;
57
58 /* state check */
59 if ((mmc_drv_obj.initialize != TRUE)
60 || (mmc_drv_obj.card_power_enable != TRUE)
61 || ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) != 0)
62 ) {
63 emmc_write_error_info(EMMC_FUNCNO_CARD_INIT, EMMC_ERR_STATE);
64 return EMMC_ERR_STATE;
65 }
66
67 /* clock on (force change) */
68 mmc_drv_obj.current_freq = 0;
69 mmc_drv_obj.max_freq = MMC_20MHZ;
70 result = emmc_set_request_mmc_clock(&freq);
71 if (result != EMMC_SUCCESS) {
72 emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT);
73 return EMMC_ERR;
74 }
75
76 rcar_micro_delay(1000U); /* wait 1ms */
77
78 /* Get current access partition */
79 emmc_get_partition_access();
80
81 /* CMD0, arg=0x00000000 */
82 result = emmc_send_idle_cmd(0x00000000);
83 if (result != EMMC_SUCCESS) {
84 emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT);
85 return result;
86 }
87
88 rcar_micro_delay(200U); /* wait 74clock 390kHz(189.74us) */
89
90 /* CMD1 */
91 emmc_make_nontrans_cmd(CMD1_SEND_OP_COND, EMMC_HOST_OCR_VALUE);
92 for (retry = 300; retry > 0; retry--) {
93 result =
94 emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
95 if (result != EMMC_SUCCESS) {
96 emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT);
97 return result;
98 }
99
100 if ((mmc_drv_obj.r3_ocr & EMMC_OCR_STATUS_BIT) != 0) {
101 break; /* card is ready. exit loop */
102 }
103 rcar_micro_delay(1000U); /* wait 1ms */
104 }
105
106 if (retry == 0) {
107 emmc_write_error_info(EMMC_FUNCNO_CARD_INIT, EMMC_ERR_TIMEOUT);
108 return EMMC_ERR_TIMEOUT;
109 }
110
111 switch (mmc_drv_obj.r3_ocr & EMMC_OCR_ACCESS_MODE_MASK) {
112 case EMMC_OCR_ACCESS_MODE_SECT:
113 mmc_drv_obj.access_mode = TRUE; /* sector mode */
114 break;
115 default:
116 /* unknown value */
117 emmc_write_error_info(EMMC_FUNCNO_CARD_INIT, EMMC_ERR);
118 return EMMC_ERR;
119 }
120
121 /* CMD2 */
122 emmc_make_nontrans_cmd(CMD2_ALL_SEND_CID_MMC, 0x00000000);
123 mmc_drv_obj.response = (uint32_t *) (&mmc_drv_obj.cid_data[0]); /* use CID special buffer */
124 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
125 if (result != EMMC_SUCCESS) {
126 emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT);
127 return result;
128 }
129
130 /* CMD3 */
131 emmc_make_nontrans_cmd(CMD3_SET_RELATIVE_ADDR, EMMC_RCA << 16);
132 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
133 if (result != EMMC_SUCCESS) {
134 emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT);
135 return result;
136 }
137
138 /* CMD9 (CSD) */
139 emmc_make_nontrans_cmd(CMD9_SEND_CSD, EMMC_RCA << 16);
140 mmc_drv_obj.response = (uint32_t *) (&mmc_drv_obj.csd_data[0]); /* use CSD special buffer */
141 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
142 if (result != EMMC_SUCCESS) {
143 emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT);
144 return result;
145 }
146
147 /* card version check */
148 if (EMMC_CSD_SPEC_VARS() < 4) {
149 emmc_write_error_info(EMMC_FUNCNO_CARD_INIT,
150 EMMC_ERR_ILLEGAL_CARD);
151 return EMMC_ERR_ILLEGAL_CARD;
152 }
153
154 /* CMD7 (select card) */
155 emmc_make_nontrans_cmd(CMD7_SELECT_CARD, EMMC_RCA << 16);
156 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
157 if (result != EMMC_SUCCESS) {
158 emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT);
159 return result;
160 }
161
162 mmc_drv_obj.selected = TRUE;
163
164 /* card speed check */
165 resultCalc = emmc_calc_tran_speed(&freq); /* Card spec is calculated from TRAN_SPEED(CSD). */
166 if (resultCalc == 0) {
167 emmc_write_error_info(EMMC_FUNCNO_CARD_INIT,
168 EMMC_ERR_ILLEGAL_CARD);
169 return EMMC_ERR_ILLEGAL_CARD;
170 }
171 mmc_drv_obj.max_freq = freq; /* max frequency (card spec) */
172
173 result = emmc_set_request_mmc_clock(&freq);
174 if (result != EMMC_SUCCESS) {
175 emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT);
176 return EMMC_ERR;
177 }
178
179 /* set read/write timeout */
180 mmc_drv_obj.data_timeout = emmc_set_timeout_register_value(freq);
181 SETR_32(SD_OPTION,
182 ((GETR_32(SD_OPTION) & ~(SD_OPTION_TIMEOUT_CNT_MASK)) |
183 mmc_drv_obj.data_timeout));
184
185 /* SET_BLOCKLEN(512byte) */
186 /* CMD16 */
187 emmc_make_nontrans_cmd(CMD16_SET_BLOCKLEN, EMMC_BLOCK_LENGTH);
188 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
189 if (result != EMMC_SUCCESS) {
190 emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT);
191 return result;
192 }
193
194 /* Transfer Data Length */
195 SETR_32(SD_SIZE, EMMC_BLOCK_LENGTH);
196
197 /* CMD8 (EXT_CSD) */
198 emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000,
199 (uint32_t *) (&mmc_drv_obj.ext_csd_data[0]),
200 EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ,
201 HAL_MEMCARD_NOT_DMA);
202 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
203 if (result != EMMC_SUCCESS) {
204 /* CMD12 is not send.
205 * If BUS initialization is failed, user must be execute Bus initialization again.
206 * Bus initialization is start CMD0(soft reset command).
207 */
208 emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT);
209 return result;
210 }
211
212 /* Set boot partition */
213 emmc_set_bootpartition();
214
215 return EMMC_SUCCESS;
216 }
217
emmc_high_speed(void)218 static EMMC_ERROR_CODE emmc_high_speed(void)
219 {
220 uint32_t freq; /**< High speed mode clock frequency */
221 EMMC_ERROR_CODE result;
222 uint8_t cardType;
223
224 /* state check */
225 if (mmc_drv_obj.selected != TRUE) {
226 emmc_write_error_info(EMMC_FUNCNO_HIGH_SPEED, EMMC_ERR_STATE);
227 return EMMC_ERR_STATE;
228 }
229
230 /* max frequency */
231 cardType = (uint8_t) mmc_drv_obj.ext_csd_data[EMMC_EXT_CSD_CARD_TYPE];
232 if ((cardType & EMMC_EXT_CSD_CARD_TYPE_52MHZ) != 0)
233 freq = MMC_52MHZ;
234 else if ((cardType & EMMC_EXT_CSD_CARD_TYPE_26MHZ) != 0)
235 freq = MMC_26MHZ;
236 else
237 freq = MMC_20MHZ;
238
239 /* Hi-Speed-mode selction */
240 if ((MMC_52MHZ == freq) || (MMC_26MHZ == freq)) {
241 /* CMD6 */
242 emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS_TIMING);
243 result =
244 emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
245 if (result != EMMC_SUCCESS) {
246 emmc_write_error_info_func_no(EMMC_FUNCNO_HIGH_SPEED);
247 return result;
248 }
249
250 mmc_drv_obj.hs_timing = TIMING_HIGH_SPEED; /* High-Speed */
251 }
252
253 /* set mmc clock */
254 mmc_drv_obj.max_freq = freq;
255 result = emmc_set_request_mmc_clock(&freq);
256 if (result != EMMC_SUCCESS) {
257 emmc_write_error_info_func_no(EMMC_FUNCNO_HIGH_SPEED);
258 return EMMC_ERR;
259 }
260
261 /* set read/write timeout */
262 mmc_drv_obj.data_timeout = emmc_set_timeout_register_value(freq);
263 SETR_32(SD_OPTION,
264 ((GETR_32(SD_OPTION) & ~(SD_OPTION_TIMEOUT_CNT_MASK)) |
265 mmc_drv_obj.data_timeout));
266
267 /* CMD13 */
268 emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16);
269 result =
270 emmc_exec_cmd(EMMC_R1_ERROR_MASK_WITHOUT_CRC, mmc_drv_obj.response);
271 if (result != EMMC_SUCCESS) {
272 emmc_write_error_info_func_no(EMMC_FUNCNO_HIGH_SPEED);
273 return result;
274 }
275
276 return EMMC_SUCCESS;
277 }
278
emmc_clock_ctrl(uint8_t mode)279 static EMMC_ERROR_CODE emmc_clock_ctrl(uint8_t mode)
280 {
281 uint32_t value;
282
283 /* busy check */
284 if ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) != 0) {
285 emmc_write_error_info(EMMC_FUNCNO_SET_CLOCK,
286 EMMC_ERR_CARD_BUSY);
287 return EMMC_ERR;
288 }
289
290 if (mode == TRUE) {
291 /* clock ON */
292 value =
293 ((GETR_32(SD_CLK_CTRL) | MMC_SD_CLK_START) &
294 SD_CLK_WRITE_MASK);
295 SETR_32(SD_CLK_CTRL, value); /* on */
296 mmc_drv_obj.clock_enable = TRUE;
297 } else {
298 /* clock OFF */
299 value =
300 ((GETR_32(SD_CLK_CTRL) & MMC_SD_CLK_STOP) &
301 SD_CLK_WRITE_MASK);
302 SETR_32(SD_CLK_CTRL, value); /* off */
303 mmc_drv_obj.clock_enable = FALSE;
304 }
305
306 return EMMC_SUCCESS;
307 }
308
emmc_bus_width(uint32_t width)309 static EMMC_ERROR_CODE emmc_bus_width(uint32_t width)
310 {
311 EMMC_ERROR_CODE result = EMMC_ERR;
312
313 /* parameter check */
314 if ((width != 8) && (width != 4) && (width != 1)) {
315 emmc_write_error_info(EMMC_FUNCNO_BUS_WIDTH, EMMC_ERR_PARAM);
316 return EMMC_ERR_PARAM;
317 }
318
319 /* state check */
320 if (mmc_drv_obj.selected != TRUE) {
321 emmc_write_error_info(EMMC_FUNCNO_BUS_WIDTH, EMMC_ERR_STATE);
322 return EMMC_ERR_STATE;
323 }
324
325 mmc_drv_obj.bus_width = (HAL_MEMCARD_DATA_WIDTH) (width >> 2); /* 2 = 8bit, 1 = 4bit, 0 =1bit */
326
327 /* CMD6 */
328 emmc_make_nontrans_cmd(CMD6_SWITCH,
329 (EMMC_SWITCH_BUS_WIDTH_1 |
330 (mmc_drv_obj.bus_width << 8)));
331 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
332 if (result != EMMC_SUCCESS) {
333 /* occurred error */
334 mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT;
335 goto EXIT;
336 }
337
338 switch (mmc_drv_obj.bus_width) {
339 case HAL_MEMCARD_DATA_WIDTH_1_BIT:
340 SETR_32(SD_OPTION,
341 ((GETR_32(SD_OPTION) & ~(BIT15 | BIT13)) | BIT15));
342 break;
343 case HAL_MEMCARD_DATA_WIDTH_4_BIT:
344 SETR_32(SD_OPTION, (GETR_32(SD_OPTION) & ~(BIT15 | BIT13)));
345 break;
346 case HAL_MEMCARD_DATA_WIDTH_8_BIT:
347 SETR_32(SD_OPTION,
348 ((GETR_32(SD_OPTION) & ~(BIT15 | BIT13)) | BIT13));
349 break;
350 default:
351 goto EXIT;
352 }
353
354 /* CMD13 */
355 emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16);
356 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
357 if (result != EMMC_SUCCESS) {
358 goto EXIT;
359 }
360
361 /* CMD8 (EXT_CSD) */
362 emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000,
363 (uint32_t *) (&mmc_drv_obj.ext_csd_data[0]),
364 EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ,
365 HAL_MEMCARD_NOT_DMA);
366 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
367 if (result != EMMC_SUCCESS) {
368 goto EXIT;
369 }
370
371 return EMMC_SUCCESS;
372
373 EXIT:
374
375 emmc_write_error_info(EMMC_FUNCNO_BUS_WIDTH, result);
376 ERROR("BL2: emmc bus_width error end\n");
377 return result;
378 }
379
emmc_select_partition(EMMC_PARTITION_ID id)380 EMMC_ERROR_CODE emmc_select_partition(EMMC_PARTITION_ID id)
381 {
382 EMMC_ERROR_CODE result;
383 uint32_t arg;
384 uint32_t partition_config;
385
386 /* state check */
387 if (mmc_drv_obj.mount != TRUE) {
388 emmc_write_error_info(EMMC_FUNCNO_NONE, EMMC_ERR_STATE);
389 return EMMC_ERR_STATE;
390 }
391
392 /* id = PARTITION_ACCESS(Bit[2:0]) */
393 if ((id & ~PARTITION_ID_MASK) != 0) {
394 emmc_write_error_info(EMMC_FUNCNO_NONE, EMMC_ERR_PARAM);
395 return EMMC_ERR_PARAM;
396 }
397
398 /* EXT_CSD[179] value */
399 partition_config =
400 (uint32_t) mmc_drv_obj.ext_csd_data[EMMC_EXT_CSD_PARTITION_CONFIG];
401 if ((partition_config & PARTITION_ID_MASK) == id) {
402 result = EMMC_SUCCESS;
403 } else {
404
405 partition_config =
406 (uint32_t) ((partition_config & ~PARTITION_ID_MASK) | id);
407 arg = EMMC_SWITCH_PARTITION_CONFIG | (partition_config << 8);
408
409 result = emmc_set_ext_csd(arg);
410 }
411
412 return result;
413 }
414
set_sd_clk(uint32_t clkDiv)415 static void set_sd_clk(uint32_t clkDiv)
416 {
417 uint32_t dataL;
418
419 dataL = (GETR_32(SD_CLK_CTRL) & (~SD_CLK_CTRL_CLKDIV_MASK));
420
421 switch (clkDiv) {
422 case 1:
423 dataL |= 0x000000FFU;
424 break; /* 1/1 */
425 case 2:
426 dataL |= 0x00000000U;
427 break; /* 1/2 */
428 case 4:
429 dataL |= 0x00000001U;
430 break; /* 1/4 */
431 case 8:
432 dataL |= 0x00000002U;
433 break; /* 1/8 */
434 case 16:
435 dataL |= 0x00000004U;
436 break; /* 1/16 */
437 case 32:
438 dataL |= 0x00000008U;
439 break; /* 1/32 */
440 case 64:
441 dataL |= 0x00000010U;
442 break; /* 1/64 */
443 case 128:
444 dataL |= 0x00000020U;
445 break; /* 1/128 */
446 case 256:
447 dataL |= 0x00000040U;
448 break; /* 1/256 */
449 case 512:
450 dataL |= 0x00000080U;
451 break; /* 1/512 */
452 }
453
454 SETR_32(SD_CLK_CTRL, dataL);
455 mmc_drv_obj.current_freq = (uint32_t) clkDiv;
456 }
457
emmc_get_partition_access(void)458 static void emmc_get_partition_access(void)
459 {
460 uint32_t reg;
461 EMMC_ERROR_CODE result;
462
463 reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
464 if ((reg == PRR_PRODUCT_H3_CUT20) || (reg == PRR_PRODUCT_M3_CUT11)) {
465 SETR_32(SD_OPTION, 0x000060EEU); /* 8 bits width */
466 /* CMD8 (EXT_CSD) */
467 emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000U,
468 (uint32_t *) (&mmc_drv_obj.ext_csd_data[0]),
469 EMMC_MAX_EXT_CSD_LENGTH,
470 HAL_MEMCARD_READ, HAL_MEMCARD_NOT_DMA);
471 mmc_drv_obj.get_partition_access_flag = TRUE;
472 result =
473 emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
474 mmc_drv_obj.get_partition_access_flag = FALSE;
475 if (result == EMMC_SUCCESS) {
476 mmc_drv_obj.partition_access =
477 (EMMC_PARTITION_ID) (mmc_drv_obj.ext_csd_data[179]
478 & PARTITION_ID_MASK);
479 } else if (result == EMMC_ERR_CMD_TIMEOUT) {
480 mmc_drv_obj.partition_access = PARTITION_ID_BOOT_1;
481 } else {
482 emmc_write_error_info(EMMC_FUNCNO_GET_PERTITION_ACCESS,
483 result);
484 panic();
485 }
486 SETR_32(SD_OPTION, 0x0000C0EEU); /* Initialize */
487 }
488 }
489
emmc_calc_tran_speed(uint32_t * freq)490 static uint32_t emmc_calc_tran_speed(uint32_t *freq)
491 {
492 const uint32_t unit[8] = { 10000, 100000, 1000000, 10000000,
493 0, 0, 0, 0 }; /**< frequency unit (1/10) */
494 const uint32_t mult[16] = { 0, 10, 12, 13, 15, 20, 26, 30, 35, 40, 45,
495 52, 55, 60, 70, 80 };
496
497 uint32_t maxFreq;
498 uint32_t result;
499 uint32_t tran_speed = EMMC_CSD_TRAN_SPEED();
500
501 /* tran_speed = 0x32
502 * unit[tran_speed&0x7] = uint[0x2] = 1000000
503 * mult[(tran_speed&0x78)>>3] = mult[0x30>>3] = mult[6] = 26
504 * 1000000 * 26 = 26000000 (26MHz)
505 */
506
507 result = 1;
508 maxFreq =
509 unit[tran_speed & EMMC_TRANSPEED_FREQ_UNIT_MASK] *
510 mult[(tran_speed & EMMC_TRANSPEED_MULT_MASK) >>
511 EMMC_TRANSPEED_MULT_SHIFT];
512
513 if (maxFreq == 0) {
514 result = 0;
515 } else if (MMC_FREQ_52MHZ <= maxFreq)
516 *freq = MMC_52MHZ;
517 else if (MMC_FREQ_26MHZ <= maxFreq)
518 *freq = MMC_26MHZ;
519 else if (MMC_FREQ_20MHZ <= maxFreq)
520 *freq = MMC_20MHZ;
521 else
522 *freq = MMC_400KHZ;
523
524 return result;
525 }
526
emmc_set_timeout_register_value(uint32_t freq)527 static uint32_t emmc_set_timeout_register_value(uint32_t freq)
528 {
529 uint32_t timeoutCnt; /* SD_OPTION - Timeout Counter */
530
531 switch (freq) {
532 case 1U:
533 timeoutCnt = 0xE0U;
534 break; /* SDCLK * 2^27 */
535 case 2U:
536 timeoutCnt = 0xE0U;
537 break; /* SDCLK * 2^27 */
538 case 4U:
539 timeoutCnt = 0xD0U;
540 break; /* SDCLK * 2^26 */
541 case 8U:
542 timeoutCnt = 0xC0U;
543 break; /* SDCLK * 2^25 */
544 case 16U:
545 timeoutCnt = 0xB0U;
546 break; /* SDCLK * 2^24 */
547 case 32U:
548 timeoutCnt = 0xA0U;
549 break; /* SDCLK * 2^23 */
550 case 64U:
551 timeoutCnt = 0x90U;
552 break; /* SDCLK * 2^22 */
553 case 128U:
554 timeoutCnt = 0x80U;
555 break; /* SDCLK * 2^21 */
556 case 256U:
557 timeoutCnt = 0x70U;
558 break; /* SDCLK * 2^20 */
559 case 512U:
560 timeoutCnt = 0x70U;
561 break; /* SDCLK * 2^20 */
562 default:
563 timeoutCnt = 0xE0U;
564 break; /* SDCLK * 2^27 */
565 }
566
567 return timeoutCnt;
568 }
569
emmc_set_ext_csd(uint32_t arg)570 EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg)
571 {
572 EMMC_ERROR_CODE result;
573
574 /* CMD6 */
575 emmc_make_nontrans_cmd(CMD6_SWITCH, arg);
576 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
577 if (result != EMMC_SUCCESS) {
578 return result;
579 }
580
581 /* CMD13 */
582 emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16);
583 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
584 if (result != EMMC_SUCCESS) {
585 return result;
586 }
587
588 /* CMD8 (EXT_CSD) */
589 emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000,
590 (uint32_t *) (&mmc_drv_obj.ext_csd_data[0]),
591 EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ,
592 HAL_MEMCARD_NOT_DMA);
593 result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
594 if (result != EMMC_SUCCESS) {
595 return result;
596 }
597 return EMMC_SUCCESS;
598 }
599
emmc_set_request_mmc_clock(uint32_t * freq)600 EMMC_ERROR_CODE emmc_set_request_mmc_clock(uint32_t *freq)
601 {
602 /* parameter check */
603 if (freq == NULL) {
604 emmc_write_error_info(EMMC_FUNCNO_SET_CLOCK, EMMC_ERR_PARAM);
605 return EMMC_ERR_PARAM;
606 }
607
608 /* state check */
609 if ((mmc_drv_obj.initialize != TRUE)
610 || (mmc_drv_obj.card_power_enable != TRUE)) {
611 emmc_write_error_info(EMMC_FUNCNO_SET_CLOCK, EMMC_ERR_STATE);
612 return EMMC_ERR_STATE;
613 }
614
615 /* clock is already running in the desired frequency. */
616 if ((mmc_drv_obj.clock_enable == TRUE)
617 && (mmc_drv_obj.current_freq == *freq)) {
618 return EMMC_SUCCESS;
619 }
620
621 /* busy check */
622 if ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) != 0) {
623 emmc_write_error_info(EMMC_FUNCNO_SET_CLOCK,
624 EMMC_ERR_CARD_BUSY);
625 return EMMC_ERR;
626 }
627
628 set_sd_clk(*freq);
629 mmc_drv_obj.clock_enable = FALSE;
630
631 return emmc_clock_ctrl(TRUE); /* clock on */
632 }
633
rcar_emmc_mount(void)634 EMMC_ERROR_CODE rcar_emmc_mount(void)
635 {
636 EMMC_ERROR_CODE result;
637
638 /* state check */
639 if ((mmc_drv_obj.initialize != TRUE)
640 || (mmc_drv_obj.card_power_enable != TRUE)
641 || ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) != 0)
642 ) {
643 emmc_write_error_info(EMMC_FUNCNO_MOUNT, EMMC_ERR_STATE);
644 return EMMC_ERR_STATE;
645 }
646
647 /* initialize card (IDLE state --> Transfer state) */
648 result = emmc_card_init();
649 if (result != EMMC_SUCCESS) {
650 emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT);
651 if (emmc_clock_ctrl(FALSE) != EMMC_SUCCESS) {
652 /* nothing to do. */
653 }
654 return result;
655 }
656
657 /* Switching high speed mode */
658 result = emmc_high_speed();
659 if (result != EMMC_SUCCESS) {
660 emmc_write_error_info_func_no(EMMC_FUNCNO_HIGH_SPEED);
661 if (emmc_clock_ctrl(FALSE) != EMMC_SUCCESS) {
662 /* nothing to do. */
663 }
664 return result;
665 }
666
667 /* Changing the data bus width */
668 result = emmc_bus_width(8);
669 if (result != EMMC_SUCCESS) {
670 emmc_write_error_info_func_no(EMMC_FUNCNO_BUS_WIDTH);
671 if (emmc_clock_ctrl(FALSE) != EMMC_SUCCESS) {
672 /* nothing to do. */
673 }
674 return result;
675 }
676
677 /* mount complete */
678 mmc_drv_obj.mount = TRUE;
679
680 return EMMC_SUCCESS;
681 }
682