1 /*
2 * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdint.h>
8 #include <lib/mmio.h>
9 #include "pfc_init_d3.h"
10 #include "rcar_def.h"
11 #include "../pfc_regs.h"
12
13 /* PFC */
14 #define GPSR0_D15 BIT(15)
15 #define GPSR0_D14 BIT(14)
16 #define GPSR0_D13 BIT(13)
17 #define GPSR0_D12 BIT(12)
18 #define GPSR0_D11 BIT(11)
19 #define GPSR0_D10 BIT(10)
20 #define GPSR0_D9 BIT(9)
21 #define GPSR0_D8 BIT(8)
22 #define GPSR0_D7 BIT(7)
23 #define GPSR0_D6 BIT(6)
24 #define GPSR0_D5 BIT(5)
25 #define GPSR0_D4 BIT(4)
26 #define GPSR0_D3 BIT(3)
27 #define GPSR0_D2 BIT(2)
28 #define GPSR0_D1 BIT(1)
29 #define GPSR0_D0 BIT(0)
30 #define GPSR1_CLKOUT BIT(28)
31 #define GPSR1_EX_WAIT0_A BIT(27)
32 #define GPSR1_WE1 BIT(26)
33 #define GPSR1_WE0 BIT(25)
34 #define GPSR1_RD_WR BIT(24)
35 #define GPSR1_RD BIT(23)
36 #define GPSR1_BS BIT(22)
37 #define GPSR1_CS1_A26 BIT(21)
38 #define GPSR1_CS0 BIT(20)
39 #define GPSR1_A19 BIT(19)
40 #define GPSR1_A18 BIT(18)
41 #define GPSR1_A17 BIT(17)
42 #define GPSR1_A16 BIT(16)
43 #define GPSR1_A15 BIT(15)
44 #define GPSR1_A14 BIT(14)
45 #define GPSR1_A13 BIT(13)
46 #define GPSR1_A12 BIT(12)
47 #define GPSR1_A11 BIT(11)
48 #define GPSR1_A10 BIT(10)
49 #define GPSR1_A9 BIT(9)
50 #define GPSR1_A8 BIT(8)
51 #define GPSR1_A7 BIT(7)
52 #define GPSR1_A6 BIT(6)
53 #define GPSR1_A5 BIT(5)
54 #define GPSR1_A4 BIT(4)
55 #define GPSR1_A3 BIT(3)
56 #define GPSR1_A2 BIT(2)
57 #define GPSR1_A1 BIT(1)
58 #define GPSR1_A0 BIT(0)
59 #define GPSR2_AVB_AVTP_CAPTURE_A BIT(14)
60 #define GPSR2_AVB_AVTP_MATCH_A BIT(13)
61 #define GPSR2_AVB_LINK BIT(12)
62 #define GPSR2_AVB_PHY_INT BIT(11)
63 #define GPSR2_AVB_MAGIC BIT(10)
64 #define GPSR2_AVB_MDC BIT(9)
65 #define GPSR2_PWM2_A BIT(8)
66 #define GPSR2_PWM1_A BIT(7)
67 #define GPSR2_PWM0 BIT(6)
68 #define GPSR2_IRQ5 BIT(5)
69 #define GPSR2_IRQ4 BIT(4)
70 #define GPSR2_IRQ3 BIT(3)
71 #define GPSR2_IRQ2 BIT(2)
72 #define GPSR2_IRQ1 BIT(1)
73 #define GPSR2_IRQ0 BIT(0)
74 #define GPSR3_SD1_WP BIT(15)
75 #define GPSR3_SD1_CD BIT(14)
76 #define GPSR3_SD0_WP BIT(13)
77 #define GPSR3_SD0_CD BIT(12)
78 #define GPSR3_SD1_DAT3 BIT(11)
79 #define GPSR3_SD1_DAT2 BIT(10)
80 #define GPSR3_SD1_DAT1 BIT(9)
81 #define GPSR3_SD1_DAT0 BIT(8)
82 #define GPSR3_SD1_CMD BIT(7)
83 #define GPSR3_SD1_CLK BIT(6)
84 #define GPSR3_SD0_DAT3 BIT(5)
85 #define GPSR3_SD0_DAT2 BIT(4)
86 #define GPSR3_SD0_DAT1 BIT(3)
87 #define GPSR3_SD0_DAT0 BIT(2)
88 #define GPSR3_SD0_CMD BIT(1)
89 #define GPSR3_SD0_CLK BIT(0)
90 #define GPSR4_SD3_DS BIT(17)
91 #define GPSR4_SD3_DAT7 BIT(16)
92 #define GPSR4_SD3_DAT6 BIT(15)
93 #define GPSR4_SD3_DAT5 BIT(14)
94 #define GPSR4_SD3_DAT4 BIT(13)
95 #define GPSR4_SD3_DAT3 BIT(12)
96 #define GPSR4_SD3_DAT2 BIT(11)
97 #define GPSR4_SD3_DAT1 BIT(10)
98 #define GPSR4_SD3_DAT0 BIT(9)
99 #define GPSR4_SD3_CMD BIT(8)
100 #define GPSR4_SD3_CLK BIT(7)
101 #define GPSR4_SD2_DS BIT(6)
102 #define GPSR4_SD2_DAT3 BIT(5)
103 #define GPSR4_SD2_DAT2 BIT(4)
104 #define GPSR4_SD2_DAT1 BIT(3)
105 #define GPSR4_SD2_DAT0 BIT(2)
106 #define GPSR4_SD2_CMD BIT(1)
107 #define GPSR4_SD2_CLK BIT(0)
108 #define GPSR5_MLB_DAT BIT(25)
109 #define GPSR5_MLB_SIG BIT(24)
110 #define GPSR5_MLB_CLK BIT(23)
111 #define GPSR5_MSIOF0_RXD BIT(22)
112 #define GPSR5_MSIOF0_SS2 BIT(21)
113 #define GPSR5_MSIOF0_TXD BIT(20)
114 #define GPSR5_MSIOF0_SS1 BIT(19)
115 #define GPSR5_MSIOF0_SYNC BIT(18)
116 #define GPSR5_MSIOF0_SCK BIT(17)
117 #define GPSR5_HRTS0 BIT(16)
118 #define GPSR5_HCTS0 BIT(15)
119 #define GPSR5_HTX0 BIT(14)
120 #define GPSR5_HRX0 BIT(13)
121 #define GPSR5_HSCK0 BIT(12)
122 #define GPSR5_RX2_A BIT(11)
123 #define GPSR5_TX2_A BIT(10)
124 #define GPSR5_SCK2 BIT(9)
125 #define GPSR5_RTS1_TANS BIT(8)
126 #define GPSR5_CTS1 BIT(7)
127 #define GPSR5_TX1_A BIT(6)
128 #define GPSR5_RX1_A BIT(5)
129 #define GPSR5_RTS0_TANS BIT(4)
130 #define GPSR5_CTS0 BIT(3)
131 #define GPSR5_TX0 BIT(2)
132 #define GPSR5_RX0 BIT(1)
133 #define GPSR5_SCK0 BIT(0)
134 #define GPSR6_USB31_OVC BIT(31)
135 #define GPSR6_USB31_PWEN BIT(30)
136 #define GPSR6_USB30_OVC BIT(29)
137 #define GPSR6_USB30_PWEN BIT(28)
138 #define GPSR6_USB1_OVC BIT(27)
139 #define GPSR6_USB1_PWEN BIT(26)
140 #define GPSR6_USB0_OVC BIT(25)
141 #define GPSR6_USB0_PWEN BIT(24)
142 #define GPSR6_AUDIO_CLKB_B BIT(23)
143 #define GPSR6_AUDIO_CLKA_A BIT(22)
144 #define GPSR6_SSI_SDATA9_A BIT(21)
145 #define GPSR6_SSI_SDATA8 BIT(20)
146 #define GPSR6_SSI_SDATA7 BIT(19)
147 #define GPSR6_SSI_WS78 BIT(18)
148 #define GPSR6_SSI_SCK78 BIT(17)
149 #define GPSR6_SSI_SDATA6 BIT(16)
150 #define GPSR6_SSI_WS6 BIT(15)
151 #define GPSR6_SSI_SCK6 BIT(14)
152 #define GPSR6_SSI_SDATA5 BIT(13)
153 #define GPSR6_SSI_WS5 BIT(12)
154 #define GPSR6_SSI_SCK5 BIT(11)
155 #define GPSR6_SSI_SDATA4 BIT(10)
156 #define GPSR6_SSI_WS4 BIT(9)
157 #define GPSR6_SSI_SCK4 BIT(8)
158 #define GPSR6_SSI_SDATA3 BIT(7)
159 #define GPSR6_SSI_WS34 BIT(6)
160 #define GPSR6_SSI_SCK34 BIT(5)
161 #define GPSR6_SSI_SDATA2_A BIT(4)
162 #define GPSR6_SSI_SDATA1_A BIT(3)
163 #define GPSR6_SSI_SDATA0 BIT(2)
164 #define GPSR6_SSI_WS0129 BIT(1)
165 #define GPSR6_SSI_SCK0129 BIT(0)
166 #define GPSR7_HDMI1_CEC BIT(3)
167 #define GPSR7_HDMI0_CEC BIT(2)
168 #define GPSR7_AVS2 BIT(1)
169 #define GPSR7_AVS1 BIT(0)
170
171 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
172 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
173 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
174 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
175 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
176 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
177 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
178 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
179
180 #define POC_SD3_DS_33V BIT(29)
181 #define POC_SD3_DAT7_33V BIT(28)
182 #define POC_SD3_DAT6_33V BIT(27)
183 #define POC_SD3_DAT5_33V BIT(26)
184 #define POC_SD3_DAT4_33V BIT(25)
185 #define POC_SD3_DAT3_33V BIT(24)
186 #define POC_SD3_DAT2_33V BIT(23)
187 #define POC_SD3_DAT1_33V BIT(22)
188 #define POC_SD3_DAT0_33V BIT(21)
189 #define POC_SD3_CMD_33V BIT(20)
190 #define POC_SD3_CLK_33V BIT(19)
191 #define POC_SD2_DS_33V BIT(18)
192 #define POC_SD2_DAT3_33V BIT(17)
193 #define POC_SD2_DAT2_33V BIT(16)
194 #define POC_SD2_DAT1_33V BIT(15)
195 #define POC_SD2_DAT0_33V BIT(14)
196 #define POC_SD2_CMD_33V BIT(13)
197 #define POC_SD2_CLK_33V BIT(12)
198 #define POC_SD1_DAT3_33V BIT(11)
199 #define POC_SD1_DAT2_33V BIT(10)
200 #define POC_SD1_DAT1_33V BIT(9)
201 #define POC_SD1_DAT0_33V BIT(8)
202 #define POC_SD1_CMD_33V BIT(7)
203 #define POC_SD1_CLK_33V BIT(6)
204 #define POC_SD0_DAT3_33V BIT(5)
205 #define POC_SD0_DAT2_33V BIT(4)
206 #define POC_SD0_DAT1_33V BIT(3)
207 #define POC_SD0_DAT0_33V BIT(2)
208 #define POC_SD0_CMD_33V BIT(1)
209 #define POC_SD0_CLK_33V BIT(0)
210
211 #define DRVCTRL0_MASK (0xCCCCCCCCU)
212 #define DRVCTRL1_MASK (0xCCCCCCC8U)
213 #define DRVCTRL2_MASK (0x88888888U)
214 #define DRVCTRL3_MASK (0x88888888U)
215 #define DRVCTRL4_MASK (0x88888888U)
216 #define DRVCTRL5_MASK (0x88888888U)
217 #define DRVCTRL6_MASK (0x88888888U)
218 #define DRVCTRL7_MASK (0x88888888U)
219 #define DRVCTRL8_MASK (0x88888888U)
220 #define DRVCTRL9_MASK (0x88888888U)
221 #define DRVCTRL10_MASK (0x88888888U)
222 #define DRVCTRL11_MASK (0x888888CCU)
223 #define DRVCTRL12_MASK (0xCCCFFFCFU)
224 #define DRVCTRL13_MASK (0xCC888888U)
225 #define DRVCTRL14_MASK (0x88888888U)
226 #define DRVCTRL15_MASK (0x88888888U)
227 #define DRVCTRL16_MASK (0x88888888U)
228 #define DRVCTRL17_MASK (0x88888888U)
229 #define DRVCTRL18_MASK (0x88888888U)
230 #define DRVCTRL19_MASK (0x88888888U)
231 #define DRVCTRL20_MASK (0x88888888U)
232 #define DRVCTRL21_MASK (0x88888888U)
233 #define DRVCTRL22_MASK (0x88888888U)
234 #define DRVCTRL23_MASK (0x88888888U)
235 #define DRVCTRL24_MASK (0x8888888FU)
236
237 #define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
238 #define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
239 #define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U)
240 #define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U)
241 #define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U)
242 #define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U)
243 #define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U)
244 #define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U)
245 #define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U)
246 #define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U)
247 #define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U)
248 #define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U)
249 #define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U)
250 #define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U)
251 #define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U)
252 #define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U)
253 #define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U)
254 #define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U)
255 #define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U)
256 #define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U)
257 #define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U)
258 #define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U)
259 #define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U)
260 #define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U)
261 #define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U)
262 #define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U)
263 #define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U)
264 #define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U)
265 #define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U)
266 #define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U)
267 #define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U)
268 #define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U)
269 #define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U)
270 #define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U)
271 #define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U)
272 #define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U)
273 #define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U)
274 #define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U)
275 #define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U)
276 #define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U)
277 #define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U)
278 #define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U)
279 #define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U)
280 #define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U)
281 #define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U)
282 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
283 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
284 #define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
285 #define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U)
286 #define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U)
287 #define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U)
288 #define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U)
289 #define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U)
290 #define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
291 #define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U)
292 #define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U)
293 #define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U)
294 #define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U)
295 #define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U)
296 #define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U)
297 #define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U)
298 #define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U)
299 #define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U)
300 #define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U)
301 #define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U)
302 #define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U)
303 #define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U)
304 #define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U)
305 #define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U)
306 #define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U)
307 #define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U)
308 #define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U)
309 #define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U)
310 #define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U)
311 #define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U)
312 #define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U)
313 #define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U)
314 #define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
315 #define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
316 #define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U)
317 #define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U)
318 #define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U)
319 #define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U)
320 #define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U)
321 #define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U)
322 #define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U)
323 #define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U)
324 #define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U)
325 #define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U)
326 #define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
327 #define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
328 #define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
329 #define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
330 #define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
331 #define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
332 #define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
333 #define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
334 #define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U)
335 #define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U)
336 #define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U)
337 #define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U)
338 #define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U)
339 #define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U)
340 #define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U)
341 #define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U)
342 #define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U)
343 #define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U)
344 #define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U)
345 #define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U)
346 #define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U)
347 #define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U)
348 #define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U)
349 #define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U)
350 #define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U)
351 #define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U)
352 #define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U)
353 #define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U)
354 #define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U)
355 #define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U)
356 #define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U)
357 #define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U)
358 #define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U)
359 #define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U)
360 #define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U)
361 #define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U)
362 #define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U)
363 #define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U)
364 #define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U)
365 #define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U)
366 #define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U)
367 #define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U)
368 #define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U)
369 #define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U)
370 #define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U)
371 #define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U)
372 #define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U)
373 #define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U)
374 #define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U)
375 #define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U)
376 #define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U)
377 #define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U)
378 #define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U)
379 #define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U)
380 #define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U)
381 #define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U)
382 #define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U)
383 #define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U)
384 #define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U)
385 #define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U)
386 #define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U)
387 #define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U)
388 #define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U)
389 #define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U)
390 #define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U)
391 #define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U)
392 #define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U)
393 #define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U)
394 #define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U)
395 #define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U)
396 #define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U)
397 #define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U)
398 #define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U)
399 #define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U)
400 #define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U)
401 #define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U)
402 #define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U)
403 #define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U)
404 #define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U)
405 #define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U)
406 #define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U)
407 #define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U)
408 #define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U)
409 #define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U)
410 #define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U)
411 #define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U)
412 #define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U)
413 #define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U)
414 #define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U)
415 #define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U)
416 #define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U)
417 #define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U)
418 #define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U)
419 #define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U)
420 #define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U)
421 #define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U)
422 #define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U)
423 #define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U)
424 #define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U)
425 #define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U)
426 #define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U)
427 #define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U)
428 #define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U)
429 #define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U)
430 #define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U)
431 #define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U)
432
433 #define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U)
434 #define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U)
435 #define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U)
436 #define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U)
437 #define MOD_SEL0_MSIOF3_E ((uint32_t)4U << 29U)
438 #define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U)
439 #define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U)
440 #define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U)
441 #define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U)
442 #define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U)
443 #define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U)
444 #define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U)
445 #define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U)
446 #define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U)
447 #define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U)
448 #define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U)
449 #define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U)
450 #define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U)
451 #define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U)
452 #define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U)
453 #define MOD_SEL0_I2C2_A ((uint32_t)0U << 21U)
454 #define MOD_SEL0_I2C2_B ((uint32_t)1U << 21U)
455 #define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U)
456 #define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U)
457 #define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 19U)
458 #define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 19U)
459 #define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 17U)
460 #define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 17U)
461 #define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 17U)
462 #define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 17U)
463 #define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 16U)
464 #define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 16U)
465 #define MOD_SEL0_FSO_A ((uint32_t)0U << 15U)
466 #define MOD_SEL0_FSO_B ((uint32_t)1U << 15U)
467 #define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 13U)
468 #define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 13U)
469 #define MOD_SEL0_HSCIF2_C ((uint32_t)2U << 13U)
470 #define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 12U)
471 #define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 12U)
472 #define MOD_SEL0_DRIF3_A ((uint32_t)0U << 11U)
473 #define MOD_SEL0_DRIF3_B ((uint32_t)1U << 11U)
474 #define MOD_SEL0_DRIF2_A ((uint32_t)0U << 10U)
475 #define MOD_SEL0_DRIF2_B ((uint32_t)1U << 10U)
476 #define MOD_SEL0_DRIF1_A ((uint32_t)0U << 8U)
477 #define MOD_SEL0_DRIF1_B ((uint32_t)1U << 8U)
478 #define MOD_SEL0_DRIF1_C ((uint32_t)2U << 8U)
479 #define MOD_SEL0_DRIF0_A ((uint32_t)0U << 6U)
480 #define MOD_SEL0_DRIF0_B ((uint32_t)1U << 6U)
481 #define MOD_SEL0_DRIF0_C ((uint32_t)2U << 6U)
482 #define MOD_SEL0_CANFD0_A ((uint32_t)0U << 5U)
483 #define MOD_SEL0_CANFD0_B ((uint32_t)1U << 5U)
484 #define MOD_SEL0_ADG_A_A ((uint32_t)0U << 3U)
485 #define MOD_SEL0_ADG_A_B ((uint32_t)1U << 3U)
486 #define MOD_SEL0_ADG_A_C ((uint32_t)2U << 3U)
487 #define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U)
488 #define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U)
489 #define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U)
490 #define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U)
491 #define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U)
492 #define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U)
493 #define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U)
494 #define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U)
495 #define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U)
496 #define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U)
497 #define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U)
498 #define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U)
499 #define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U)
500 #define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U)
501 #define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U)
502 #define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U)
503 #define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U)
504 #define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U)
505 #define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U)
506 #define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U)
507 #define MOD_SEL1_SSI_A ((uint32_t)0U << 20U)
508 #define MOD_SEL1_SSI_B ((uint32_t)1U << 20U)
509 #define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U)
510 #define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U)
511 #define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U)
512 #define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U)
513 #define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U)
514 #define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U)
515 #define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U)
516 #define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U)
517 #define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U)
518 #define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U)
519 #define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U)
520 #define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
521 #define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
522 #define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U)
523 #define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U)
524 #define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U)
525 #define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U)
526 #define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U)
527 #define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U)
528 #define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U)
529 #define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U)
530 #define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U)
531 #define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U)
532 #define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U)
533 #define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U)
534 #define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U)
535 #define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U)
536 #define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U)
537 #define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U)
538 #define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U)
539 #define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U)
540 #define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U)
541 #define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U)
542 #define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U)
543 #define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U)
544 #define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U)
545 #define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U)
546 #define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U)
547 #define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U)
548 #define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U)
549 #define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U)
550 #define MOD_SEL2_FM_A ((uint32_t)0U << 27U)
551 #define MOD_SEL2_FM_B ((uint32_t)1U << 27U)
552 #define MOD_SEL2_FM_C ((uint32_t)2U << 27U)
553 #define MOD_SEL2_FM_D ((uint32_t)3U << 27U)
554 #define MOD_SEL2_SCIF5_A ((uint32_t)0U << 26U)
555 #define MOD_SEL2_SCIF5_B ((uint32_t)1U << 26U)
556 #define MOD_SEL2_I2C6_A ((uint32_t)0U << 23U)
557 #define MOD_SEL2_I2C6_B ((uint32_t)1U << 23U)
558 #define MOD_SEL2_I2C6_C ((uint32_t)2U << 23U)
559 #define MOD_SEL2_NDF_A ((uint32_t)0U << 22U)
560 #define MOD_SEL2_NDF_B ((uint32_t)1U << 22U)
561 #define MOD_SEL2_SSI2_A ((uint32_t)0U << 21U)
562 #define MOD_SEL2_SSI2_B ((uint32_t)1U << 21U)
563 #define MOD_SEL2_SSI9_A ((uint32_t)0U << 20U)
564 #define MOD_SEL2_SSI9_B ((uint32_t)1U << 20U)
565 #define MOD_SEL2_TIMER_TMU2_A ((uint32_t)0U << 19U)
566 #define MOD_SEL2_TIMER_TMU2_B ((uint32_t)1U << 19U)
567 #define MOD_SEL2_ADG_B_A ((uint32_t)0U << 18U)
568 #define MOD_SEL2_ADG_B_B ((uint32_t)1U << 18U)
569 #define MOD_SEL2_ADG_C_A ((uint32_t)0U << 17U)
570 #define MOD_SEL2_ADG_C_B ((uint32_t)1U << 17U)
571 #define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U)
572 #define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U)
573
pfc_reg_write(uint32_t addr,uint32_t data)574 static void pfc_reg_write(uint32_t addr, uint32_t data)
575 {
576 mmio_write_32(PFC_PMMR, ~data);
577 mmio_write_32((uintptr_t)addr, data);
578 }
579
pfc_init_d3(void)580 void pfc_init_d3(void)
581 {
582 /* initialize module select */
583 pfc_reg_write(PFC_MOD_SEL0, 0x00000000U);
584 pfc_reg_write(PFC_MOD_SEL1, 0x00000000U);
585
586 /* initialize peripheral function select */
587 pfc_reg_write(PFC_IPSR0, 0x00000001U);
588 pfc_reg_write(PFC_IPSR1, 0x00000000U);
589 pfc_reg_write(PFC_IPSR2, 0x00000000U);
590 pfc_reg_write(PFC_IPSR3, 0x00000000U);
591 pfc_reg_write(PFC_IPSR4, 0x00002000U);
592 pfc_reg_write(PFC_IPSR5, 0x00000000U);
593 pfc_reg_write(PFC_IPSR6, 0x00000000U);
594 pfc_reg_write(PFC_IPSR7, 0x00000000U);
595 pfc_reg_write(PFC_IPSR8, 0x11003301U);
596 pfc_reg_write(PFC_IPSR9, 0x11111111U);
597 pfc_reg_write(PFC_IPSR10, 0x00020000U);
598 pfc_reg_write(PFC_IPSR11, 0x40001110U);
599 pfc_reg_write(PFC_IPSR12, 0x00000000U);
600 pfc_reg_write(PFC_IPSR13, 0x00000000U);
601
602 /* initialize GPIO/perihperal function select */
603 pfc_reg_write(PFC_GPSR0, 0x0000001FU);
604 pfc_reg_write(PFC_GPSR1, 0x3FFFFFFFU);
605 pfc_reg_write(PFC_GPSR2, 0xFFFFFFFFU);
606 pfc_reg_write(PFC_GPSR3, 0x000003FFU);
607 pfc_reg_write(PFC_GPSR4, 0xFC7F0F7EU);
608 pfc_reg_write(PFC_GPSR5, 0x001BFFFBU);
609 pfc_reg_write(PFC_GPSR6, 0x00003FFFU);
610
611 /* initialize POC control register */
612 pfc_reg_write(PFC_POCCTRL0, 0xC00FFFFFU);
613 pfc_reg_write(PFC_POCCTRL2, 0XFFFFFFFEU);
614 pfc_reg_write(PFC_TDSELCTRL0, 0x00000000U);
615
616 /* initialize LSI pin pull-up/down control */
617 pfc_reg_write(PFC_PUD0, 0x0047C1A2U);
618 pfc_reg_write(PFC_PUD1, 0x4E13ABFFU);
619 pfc_reg_write(PFC_PUD2, 0xFFFFFFFFU);
620 pfc_reg_write(PFC_PUD3, 0xFF0FFFFFU);
621 pfc_reg_write(PFC_PUD4, 0xE0000000U);
622 pfc_reg_write(PFC_PUD5, 0x60000000U);
623
624 /* initialize LSI pin pull-enable register */
625 pfc_reg_write(PFC_PUEN0, 0x00000000U);
626 pfc_reg_write(PFC_PUEN1, 0x00000000U);
627 pfc_reg_write(PFC_PUEN2, 0x00000000U);
628 pfc_reg_write(PFC_PUEN3, 0x000F008CU);
629 pfc_reg_write(PFC_PUEN4, 0x00000000U);
630 pfc_reg_write(PFC_PUEN5, 0x00000000U);
631
632 /* initialize positive/negative logic select */
633 mmio_write_32(GPIO_POSNEG0, 0x00000000U);
634 mmio_write_32(GPIO_POSNEG1, 0x00000000U);
635 mmio_write_32(GPIO_POSNEG2, 0x00000000U);
636 mmio_write_32(GPIO_POSNEG3, 0x00000000U);
637 mmio_write_32(GPIO_POSNEG4, 0x00000000U);
638 mmio_write_32(GPIO_POSNEG5, 0x00000000U);
639 mmio_write_32(GPIO_POSNEG6, 0x00000000U);
640
641 /* initialize general IO/interrupt switching */
642 mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
643 mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
644 mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
645 mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
646 mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
647 mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
648 mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
649
650 /* initialize general output register */
651 mmio_write_32(GPIO_OUTDT0, 0x00000000U);
652 mmio_write_32(GPIO_OUTDT1, 0x00000000U);
653 mmio_write_32(GPIO_OUTDT2, 0x00000400U);
654 mmio_write_32(GPIO_OUTDT3, 0x00000000U);
655 mmio_write_32(GPIO_OUTDT4, 0x00000000U);
656 mmio_write_32(GPIO_OUTDT5, 0x00000006U);
657 mmio_write_32(GPIO_OUTDT6, 0x00003880U);
658
659 /* initialize general input/output switching */
660 mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
661 mmio_write_32(GPIO_INOUTSEL1, 0x00000000U);
662 mmio_write_32(GPIO_INOUTSEL2, 0x00000000U);
663 mmio_write_32(GPIO_INOUTSEL3, 0x00000000U);
664 mmio_write_32(GPIO_INOUTSEL4, 0x00802000U);
665 mmio_write_32(GPIO_INOUTSEL5, 0x00000000U);
666 mmio_write_32(GPIO_INOUTSEL6, 0x00000000U);
667 }
668