1 /*
2 * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdint.h> /* for uint32_t */
8 #include <lib/mmio.h>
9 #include "pfc_init_h3_v2.h"
10 #include "rcar_def.h"
11 #include "../pfc_regs.h"
12
13 #define GPSR0_D15 BIT(15)
14 #define GPSR0_D14 BIT(14)
15 #define GPSR0_D13 BIT(13)
16 #define GPSR0_D12 BIT(12)
17 #define GPSR0_D11 BIT(11)
18 #define GPSR0_D10 BIT(10)
19 #define GPSR0_D9 BIT(9)
20 #define GPSR0_D8 BIT(8)
21 #define GPSR0_D7 BIT(7)
22 #define GPSR0_D6 BIT(6)
23 #define GPSR0_D5 BIT(5)
24 #define GPSR0_D4 BIT(4)
25 #define GPSR0_D3 BIT(3)
26 #define GPSR0_D2 BIT(2)
27 #define GPSR0_D1 BIT(1)
28 #define GPSR0_D0 BIT(0)
29 #define GPSR1_CLKOUT BIT(28)
30 #define GPSR1_EX_WAIT0_A BIT(27)
31 #define GPSR1_WE1 BIT(26)
32 #define GPSR1_WE0 BIT(25)
33 #define GPSR1_RD_WR BIT(24)
34 #define GPSR1_RD BIT(23)
35 #define GPSR1_BS BIT(22)
36 #define GPSR1_CS1_A26 BIT(21)
37 #define GPSR1_CS0 BIT(20)
38 #define GPSR1_A19 BIT(19)
39 #define GPSR1_A18 BIT(18)
40 #define GPSR1_A17 BIT(17)
41 #define GPSR1_A16 BIT(16)
42 #define GPSR1_A15 BIT(15)
43 #define GPSR1_A14 BIT(14)
44 #define GPSR1_A13 BIT(13)
45 #define GPSR1_A12 BIT(12)
46 #define GPSR1_A11 BIT(11)
47 #define GPSR1_A10 BIT(10)
48 #define GPSR1_A9 BIT(9)
49 #define GPSR1_A8 BIT(8)
50 #define GPSR1_A7 BIT(7)
51 #define GPSR1_A6 BIT(6)
52 #define GPSR1_A5 BIT(5)
53 #define GPSR1_A4 BIT(4)
54 #define GPSR1_A3 BIT(3)
55 #define GPSR1_A2 BIT(2)
56 #define GPSR1_A1 BIT(1)
57 #define GPSR1_A0 BIT(0)
58 #define GPSR2_AVB_AVTP_CAPTURE_A BIT(14)
59 #define GPSR2_AVB_AVTP_MATCH_A BIT(13)
60 #define GPSR2_AVB_LINK BIT(12)
61 #define GPSR2_AVB_PHY_INT BIT(11)
62 #define GPSR2_AVB_MAGIC BIT(10)
63 #define GPSR2_AVB_MDC BIT(9)
64 #define GPSR2_PWM2_A BIT(8)
65 #define GPSR2_PWM1_A BIT(7)
66 #define GPSR2_PWM0 BIT(6)
67 #define GPSR2_IRQ5 BIT(5)
68 #define GPSR2_IRQ4 BIT(4)
69 #define GPSR2_IRQ3 BIT(3)
70 #define GPSR2_IRQ2 BIT(2)
71 #define GPSR2_IRQ1 BIT(1)
72 #define GPSR2_IRQ0 BIT(0)
73 #define GPSR3_SD1_WP BIT(15)
74 #define GPSR3_SD1_CD BIT(14)
75 #define GPSR3_SD0_WP BIT(13)
76 #define GPSR3_SD0_CD BIT(12)
77 #define GPSR3_SD1_DAT3 BIT(11)
78 #define GPSR3_SD1_DAT2 BIT(10)
79 #define GPSR3_SD1_DAT1 BIT(9)
80 #define GPSR3_SD1_DAT0 BIT(8)
81 #define GPSR3_SD1_CMD BIT(7)
82 #define GPSR3_SD1_CLK BIT(6)
83 #define GPSR3_SD0_DAT3 BIT(5)
84 #define GPSR3_SD0_DAT2 BIT(4)
85 #define GPSR3_SD0_DAT1 BIT(3)
86 #define GPSR3_SD0_DAT0 BIT(2)
87 #define GPSR3_SD0_CMD BIT(1)
88 #define GPSR3_SD0_CLK BIT(0)
89 #define GPSR4_SD3_DS BIT(17)
90 #define GPSR4_SD3_DAT7 BIT(16)
91 #define GPSR4_SD3_DAT6 BIT(15)
92 #define GPSR4_SD3_DAT5 BIT(14)
93 #define GPSR4_SD3_DAT4 BIT(13)
94 #define GPSR4_SD3_DAT3 BIT(12)
95 #define GPSR4_SD3_DAT2 BIT(11)
96 #define GPSR4_SD3_DAT1 BIT(10)
97 #define GPSR4_SD3_DAT0 BIT(9)
98 #define GPSR4_SD3_CMD BIT(8)
99 #define GPSR4_SD3_CLK BIT(7)
100 #define GPSR4_SD2_DS BIT(6)
101 #define GPSR4_SD2_DAT3 BIT(5)
102 #define GPSR4_SD2_DAT2 BIT(4)
103 #define GPSR4_SD2_DAT1 BIT(3)
104 #define GPSR4_SD2_DAT0 BIT(2)
105 #define GPSR4_SD2_CMD BIT(1)
106 #define GPSR4_SD2_CLK BIT(0)
107 #define GPSR5_MLB_DAT BIT(25)
108 #define GPSR5_MLB_SIG BIT(24)
109 #define GPSR5_MLB_CLK BIT(23)
110 #define GPSR5_MSIOF0_RXD BIT(22)
111 #define GPSR5_MSIOF0_SS2 BIT(21)
112 #define GPSR5_MSIOF0_TXD BIT(20)
113 #define GPSR5_MSIOF0_SS1 BIT(19)
114 #define GPSR5_MSIOF0_SYNC BIT(18)
115 #define GPSR5_MSIOF0_SCK BIT(17)
116 #define GPSR5_HRTS0 BIT(16)
117 #define GPSR5_HCTS0 BIT(15)
118 #define GPSR5_HTX0 BIT(14)
119 #define GPSR5_HRX0 BIT(13)
120 #define GPSR5_HSCK0 BIT(12)
121 #define GPSR5_RX2_A BIT(11)
122 #define GPSR5_TX2_A BIT(10)
123 #define GPSR5_SCK2 BIT(9)
124 #define GPSR5_RTS1 BIT(8)
125 #define GPSR5_CTS1 BIT(7)
126 #define GPSR5_TX1_A BIT(6)
127 #define GPSR5_RX1_A BIT(5)
128 #define GPSR5_RTS0 BIT(4)
129 #define GPSR5_CTS0 BIT(3)
130 #define GPSR5_TX0 BIT(2)
131 #define GPSR5_RX0 BIT(1)
132 #define GPSR5_SCK0 BIT(0)
133 #define GPSR6_USB31_OVC BIT(31)
134 #define GPSR6_USB31_PWEN BIT(30)
135 #define GPSR6_USB30_OVC BIT(29)
136 #define GPSR6_USB30_PWEN BIT(28)
137 #define GPSR6_USB1_OVC BIT(27)
138 #define GPSR6_USB1_PWEN BIT(26)
139 #define GPSR6_USB0_OVC BIT(25)
140 #define GPSR6_USB0_PWEN BIT(24)
141 #define GPSR6_AUDIO_CLKB_B BIT(23)
142 #define GPSR6_AUDIO_CLKA_A BIT(22)
143 #define GPSR6_SSI_SDATA9_A BIT(21)
144 #define GPSR6_SSI_SDATA8 BIT(20)
145 #define GPSR6_SSI_SDATA7 BIT(19)
146 #define GPSR6_SSI_WS78 BIT(18)
147 #define GPSR6_SSI_SCK78 BIT(17)
148 #define GPSR6_SSI_SDATA6 BIT(16)
149 #define GPSR6_SSI_WS6 BIT(15)
150 #define GPSR6_SSI_SCK6 BIT(14)
151 #define GPSR6_SSI_SDATA5 BIT(13)
152 #define GPSR6_SSI_WS5 BIT(12)
153 #define GPSR6_SSI_SCK5 BIT(11)
154 #define GPSR6_SSI_SDATA4 BIT(10)
155 #define GPSR6_SSI_WS4 BIT(9)
156 #define GPSR6_SSI_SCK4 BIT(8)
157 #define GPSR6_SSI_SDATA3 BIT(7)
158 #define GPSR6_SSI_WS34 BIT(6)
159 #define GPSR6_SSI_SCK34 BIT(5)
160 #define GPSR6_SSI_SDATA2_A BIT(4)
161 #define GPSR6_SSI_SDATA1_A BIT(3)
162 #define GPSR6_SSI_SDATA0 BIT(2)
163 #define GPSR6_SSI_WS0129 BIT(1)
164 #define GPSR6_SSI_SCK0129 BIT(0)
165 #define GPSR7_AVS2 BIT(1)
166 #define GPSR7_AVS1 BIT(0)
167
168 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
169 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
170 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
171 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
172 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
173 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
174 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
175 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
176
177 #define POC_SD3_DS_33V BIT(29)
178 #define POC_SD3_DAT7_33V BIT(28)
179 #define POC_SD3_DAT6_33V BIT(27)
180 #define POC_SD3_DAT5_33V BIT(26)
181 #define POC_SD3_DAT4_33V BIT(25)
182 #define POC_SD3_DAT3_33V BIT(24)
183 #define POC_SD3_DAT2_33V BIT(23)
184 #define POC_SD3_DAT1_33V BIT(22)
185 #define POC_SD3_DAT0_33V BIT(21)
186 #define POC_SD3_CMD_33V BIT(20)
187 #define POC_SD3_CLK_33V BIT(19)
188 #define POC_SD2_DS_33V BIT(18)
189 #define POC_SD2_DAT3_33V BIT(17)
190 #define POC_SD2_DAT2_33V BIT(16)
191 #define POC_SD2_DAT1_33V BIT(15)
192 #define POC_SD2_DAT0_33V BIT(14)
193 #define POC_SD2_CMD_33V BIT(13)
194 #define POC_SD2_CLK_33V BIT(12)
195 #define POC_SD1_DAT3_33V BIT(11)
196 #define POC_SD1_DAT2_33V BIT(10)
197 #define POC_SD1_DAT1_33V BIT(9)
198 #define POC_SD1_DAT0_33V BIT(8)
199 #define POC_SD1_CMD_33V BIT(7)
200 #define POC_SD1_CLK_33V BIT(6)
201 #define POC_SD0_DAT3_33V BIT(5)
202 #define POC_SD0_DAT2_33V BIT(4)
203 #define POC_SD0_DAT1_33V BIT(3)
204 #define POC_SD0_DAT0_33V BIT(2)
205 #define POC_SD0_CMD_33V BIT(1)
206 #define POC_SD0_CLK_33V BIT(0)
207
208 #define DRVCTRL0_MASK (0xCCCCCCCCU)
209 #define DRVCTRL1_MASK (0xCCCCCCC8U)
210 #define DRVCTRL2_MASK (0x88888888U)
211 #define DRVCTRL3_MASK (0x88888888U)
212 #define DRVCTRL4_MASK (0x88888888U)
213 #define DRVCTRL5_MASK (0x88888888U)
214 #define DRVCTRL6_MASK (0x88888888U)
215 #define DRVCTRL7_MASK (0x88888888U)
216 #define DRVCTRL8_MASK (0x88888888U)
217 #define DRVCTRL9_MASK (0x88888888U)
218 #define DRVCTRL10_MASK (0x88888888U)
219 #define DRVCTRL11_MASK (0x888888CCU)
220 #define DRVCTRL12_MASK (0xCCCFFFCFU)
221 #define DRVCTRL13_MASK (0xCC888888U)
222 #define DRVCTRL14_MASK (0x88888888U)
223 #define DRVCTRL15_MASK (0x88888888U)
224 #define DRVCTRL16_MASK (0x88888888U)
225 #define DRVCTRL17_MASK (0x88888888U)
226 #define DRVCTRL18_MASK (0x88888888U)
227 #define DRVCTRL19_MASK (0x88888888U)
228 #define DRVCTRL20_MASK (0x88888888U)
229 #define DRVCTRL21_MASK (0x88888888U)
230 #define DRVCTRL22_MASK (0x88888888U)
231 #define DRVCTRL23_MASK (0x88888888U)
232 #define DRVCTRL24_MASK (0x8888888FU)
233
234 #define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
235 #define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
236 #define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U)
237 #define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U)
238 #define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U)
239 #define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U)
240 #define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U)
241 #define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U)
242 #define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U)
243 #define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U)
244 #define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U)
245 #define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U)
246 #define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U)
247 #define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U)
248 #define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U)
249 #define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U)
250 #define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U)
251 #define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U)
252 #define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U)
253 #define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U)
254 #define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U)
255 #define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U)
256 #define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U)
257 #define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U)
258 #define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U)
259 #define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U)
260 #define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U)
261 #define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U)
262 #define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U)
263 #define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U)
264 #define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U)
265 #define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U)
266 #define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U)
267 #define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U)
268 #define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U)
269 #define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U)
270 #define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U)
271 #define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U)
272 #define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U)
273 #define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U)
274 #define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U)
275 #define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U)
276 #define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U)
277 #define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U)
278 #define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U)
279 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
280 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
281 #define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
282 #define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U)
283 #define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U)
284 #define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U)
285 #define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U)
286 #define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U)
287 #define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
288 #define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U)
289 #define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U)
290 #define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U)
291 #define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U)
292 #define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U)
293 #define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U)
294 #define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U)
295 #define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U)
296 #define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U)
297 #define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U)
298 #define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U)
299 #define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U)
300 #define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U)
301 #define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U)
302 #define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U)
303 #define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U)
304 #define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U)
305 #define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U)
306 #define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U)
307 #define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U)
308 #define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U)
309 #define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U)
310 #define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U)
311 #define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
312 #define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
313 #define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U)
314 #define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U)
315 #define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U)
316 #define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U)
317 #define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U)
318 #define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U)
319 #define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U)
320 #define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U)
321 #define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U)
322 #define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U)
323 #define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
324 #define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
325 #define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
326 #define DRVCTRL11_GP7_02(x) ((uint32_t)(x) << 12U)
327 #define DRVCTRL11_GP7_03(x) ((uint32_t)(x) << 8U)
328 #define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
329 #define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
330 #define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
331 #define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U)
332 #define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U)
333 #define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U)
334 #define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U)
335 #define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U)
336 #define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U)
337 #define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U)
338 #define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U)
339 #define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U)
340 #define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U)
341 #define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U)
342 #define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U)
343 #define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U)
344 #define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U)
345 #define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U)
346 #define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U)
347 #define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U)
348 #define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U)
349 #define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U)
350 #define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U)
351 #define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U)
352 #define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U)
353 #define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U)
354 #define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U)
355 #define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U)
356 #define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U)
357 #define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U)
358 #define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U)
359 #define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U)
360 #define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U)
361 #define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U)
362 #define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U)
363 #define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U)
364 #define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U)
365 #define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U)
366 #define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U)
367 #define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U)
368 #define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U)
369 #define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U)
370 #define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U)
371 #define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U)
372 #define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U)
373 #define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U)
374 #define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U)
375 #define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U)
376 #define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U)
377 #define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U)
378 #define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U)
379 #define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U)
380 #define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U)
381 #define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U)
382 #define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U)
383 #define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U)
384 #define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U)
385 #define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U)
386 #define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U)
387 #define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U)
388 #define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U)
389 #define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U)
390 #define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U)
391 #define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U)
392 #define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U)
393 #define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U)
394 #define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U)
395 #define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U)
396 #define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U)
397 #define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U)
398 #define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U)
399 #define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U)
400 #define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U)
401 #define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U)
402 #define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U)
403 #define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U)
404 #define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U)
405 #define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U)
406 #define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U)
407 #define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U)
408 #define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U)
409 #define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U)
410 #define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U)
411 #define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U)
412 #define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U)
413 #define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U)
414 #define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U)
415 #define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U)
416 #define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U)
417 #define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U)
418 #define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U)
419 #define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U)
420 #define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U)
421 #define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U)
422 #define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U)
423 #define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U)
424 #define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U)
425 #define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U)
426 #define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U)
427 #define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U)
428 #define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U)
429
430 #define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U)
431 #define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U)
432 #define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U)
433 #define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U)
434 #define MOD_SEL0_MSIOF3_E ((uint32_t)4U << 29U)
435 #define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U)
436 #define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U)
437 #define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U)
438 #define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U)
439 #define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U)
440 #define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U)
441 #define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U)
442 #define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U)
443 #define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U)
444 #define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U)
445 #define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U)
446 #define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U)
447 #define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U)
448 #define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U)
449 #define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U)
450 #define MOD_SEL0_I2C2_A ((uint32_t)0U << 21U)
451 #define MOD_SEL0_I2C2_B ((uint32_t)1U << 21U)
452 #define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U)
453 #define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U)
454 #define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 19U)
455 #define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 19U)
456 #define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 17U)
457 #define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 17U)
458 #define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 17U)
459 #define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 17U)
460 #define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 16U)
461 #define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 16U)
462 #define MOD_SEL0_FSO_A ((uint32_t)0U << 15U)
463 #define MOD_SEL0_FSO_B ((uint32_t)1U << 15U)
464 #define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 13U)
465 #define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 13U)
466 #define MOD_SEL0_HSCIF2_C ((uint32_t)2U << 13U)
467 #define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 12U)
468 #define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 12U)
469 #define MOD_SEL0_DRIF3_A ((uint32_t)0U << 11U)
470 #define MOD_SEL0_DRIF3_B ((uint32_t)1U << 11U)
471 #define MOD_SEL0_DRIF2_A ((uint32_t)0U << 10U)
472 #define MOD_SEL0_DRIF2_B ((uint32_t)1U << 10U)
473 #define MOD_SEL0_DRIF1_A ((uint32_t)0U << 8U)
474 #define MOD_SEL0_DRIF1_B ((uint32_t)1U << 8U)
475 #define MOD_SEL0_DRIF1_C ((uint32_t)2U << 8U)
476 #define MOD_SEL0_DRIF0_A ((uint32_t)0U << 6U)
477 #define MOD_SEL0_DRIF0_B ((uint32_t)1U << 6U)
478 #define MOD_SEL0_DRIF0_C ((uint32_t)2U << 6U)
479 #define MOD_SEL0_CANFD0_A ((uint32_t)0U << 5U)
480 #define MOD_SEL0_CANFD0_B ((uint32_t)1U << 5U)
481 #define MOD_SEL0_ADG_A_A ((uint32_t)0U << 3U)
482 #define MOD_SEL0_ADG_A_B ((uint32_t)1U << 3U)
483 #define MOD_SEL0_ADG_A_C ((uint32_t)2U << 3U)
484 #define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U)
485 #define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U)
486 #define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U)
487 #define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U)
488 #define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U)
489 #define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U)
490 #define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U)
491 #define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U)
492 #define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U)
493 #define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U)
494 #define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U)
495 #define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U)
496 #define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U)
497 #define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U)
498 #define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U)
499 #define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U)
500 #define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U)
501 #define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U)
502 #define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U)
503 #define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U)
504 #define MOD_SEL1_SSI_A ((uint32_t)0U << 20U)
505 #define MOD_SEL1_SSI_B ((uint32_t)1U << 20U)
506 #define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U)
507 #define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U)
508 #define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U)
509 #define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U)
510 #define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U)
511 #define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U)
512 #define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U)
513 #define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U)
514 #define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U)
515 #define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U)
516 #define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U)
517 #define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
518 #define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
519 #define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U)
520 #define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U)
521 #define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U)
522 #define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U)
523 #define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U)
524 #define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U)
525 #define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U)
526 #define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U)
527 #define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U)
528 #define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U)
529 #define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U)
530 #define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U)
531 #define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U)
532 #define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U)
533 #define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U)
534 #define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U)
535 #define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U)
536 #define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U)
537 #define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U)
538 #define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U)
539 #define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U)
540 #define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U)
541 #define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U)
542 #define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U)
543 #define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U)
544 #define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U)
545 #define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U)
546 #define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U)
547 #define MOD_SEL2_FM_A ((uint32_t)0U << 27U)
548 #define MOD_SEL2_FM_B ((uint32_t)1U << 27U)
549 #define MOD_SEL2_FM_C ((uint32_t)2U << 27U)
550 #define MOD_SEL2_FM_D ((uint32_t)3U << 27U)
551 #define MOD_SEL2_SCIF5_A ((uint32_t)0U << 26U)
552 #define MOD_SEL2_SCIF5_B ((uint32_t)1U << 26U)
553 #define MOD_SEL2_I2C6_A ((uint32_t)0U << 23U)
554 #define MOD_SEL2_I2C6_B ((uint32_t)1U << 23U)
555 #define MOD_SEL2_I2C6_C ((uint32_t)2U << 23U)
556 #define MOD_SEL2_NDF_A ((uint32_t)0U << 22U)
557 #define MOD_SEL2_NDF_B ((uint32_t)1U << 22U)
558 #define MOD_SEL2_SSI2_A ((uint32_t)0U << 21U)
559 #define MOD_SEL2_SSI2_B ((uint32_t)1U << 21U)
560 #define MOD_SEL2_SSI9_A ((uint32_t)0U << 20U)
561 #define MOD_SEL2_SSI9_B ((uint32_t)1U << 20U)
562 #define MOD_SEL2_TIMER_TMU2_A ((uint32_t)0U << 19U)
563 #define MOD_SEL2_TIMER_TMU2_B ((uint32_t)1U << 19U)
564 #define MOD_SEL2_ADG_B_A ((uint32_t)0U << 18U)
565 #define MOD_SEL2_ADG_B_B ((uint32_t)1U << 18U)
566 #define MOD_SEL2_ADG_C_A ((uint32_t)0U << 17U)
567 #define MOD_SEL2_ADG_C_B ((uint32_t)1U << 17U)
568 #define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U)
569 #define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U)
570
pfc_reg_write(uint32_t addr,uint32_t data)571 static void pfc_reg_write(uint32_t addr, uint32_t data)
572 {
573 mmio_write_32(PFC_PMMR, ~data);
574 mmio_write_32((uintptr_t)addr, data);
575 }
576
pfc_init_h3_v2(void)577 void pfc_init_h3_v2(void)
578 {
579 uint32_t reg;
580
581 /* initialize module select */
582 pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A
583 | MOD_SEL0_MSIOF2_A
584 | MOD_SEL0_MSIOF1_A
585 | MOD_SEL0_LBSC_A
586 | MOD_SEL0_IEBUS_A
587 | MOD_SEL0_I2C2_A
588 | MOD_SEL0_I2C1_A
589 | MOD_SEL0_HSCIF4_A
590 | MOD_SEL0_HSCIF3_A
591 | MOD_SEL0_HSCIF1_A
592 | MOD_SEL0_FSO_A
593 | MOD_SEL0_HSCIF2_A
594 | MOD_SEL0_ETHERAVB_A
595 | MOD_SEL0_DRIF3_A
596 | MOD_SEL0_DRIF2_A
597 | MOD_SEL0_DRIF1_A
598 | MOD_SEL0_DRIF0_A
599 | MOD_SEL0_CANFD0_A
600 | MOD_SEL0_ADG_A_A);
601 pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
602 | MOD_SEL1_TSIF0_A
603 | MOD_SEL1_TIMER_TMU_A
604 | MOD_SEL1_SSP1_1_A
605 | MOD_SEL1_SSP1_0_A
606 | MOD_SEL1_SSI_A
607 | MOD_SEL1_SPEED_PULSE_IF_A
608 | MOD_SEL1_SIMCARD_A
609 | MOD_SEL1_SDHI2_A
610 | MOD_SEL1_SCIF4_A
611 | MOD_SEL1_SCIF3_A
612 | MOD_SEL1_SCIF2_A
613 | MOD_SEL1_SCIF1_A
614 | MOD_SEL1_SCIF_A
615 | MOD_SEL1_REMOCON_A
616 | MOD_SEL1_RCAN0_A
617 | MOD_SEL1_PWM6_A
618 | MOD_SEL1_PWM5_A
619 | MOD_SEL1_PWM4_A
620 | MOD_SEL1_PWM3_A
621 | MOD_SEL1_PWM2_A
622 | MOD_SEL1_PWM1_A);
623 pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
624 | MOD_SEL2_I2C_3_A
625 | MOD_SEL2_I2C_0_A
626 | MOD_SEL2_FM_A
627 | MOD_SEL2_SCIF5_A
628 | MOD_SEL2_I2C6_A
629 | MOD_SEL2_NDF_A
630 | MOD_SEL2_SSI2_A
631 | MOD_SEL2_SSI9_A
632 | MOD_SEL2_TIMER_TMU2_A
633 | MOD_SEL2_ADG_B_A
634 | MOD_SEL2_ADG_C_A
635 | MOD_SEL2_VIN4_A);
636
637 /* initialize peripheral function select */
638 pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
639 | IPSR_24_FUNC(0)
640 | IPSR_20_FUNC(0)
641 | IPSR_16_FUNC(0)
642 | IPSR_12_FUNC(0)
643 | IPSR_8_FUNC(0)
644 | IPSR_4_FUNC(0)
645 | IPSR_0_FUNC(0));
646 pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6)
647 | IPSR_24_FUNC(0)
648 | IPSR_20_FUNC(0)
649 | IPSR_16_FUNC(0)
650 | IPSR_12_FUNC(3)
651 | IPSR_8_FUNC(3)
652 | IPSR_4_FUNC(3)
653 | IPSR_0_FUNC(3));
654 pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
655 | IPSR_24_FUNC(6)
656 | IPSR_20_FUNC(6)
657 | IPSR_16_FUNC(6)
658 | IPSR_12_FUNC(6)
659 | IPSR_8_FUNC(6)
660 | IPSR_4_FUNC(6)
661 | IPSR_0_FUNC(6));
662 pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6)
663 | IPSR_24_FUNC(6)
664 | IPSR_20_FUNC(6)
665 | IPSR_16_FUNC(6)
666 | IPSR_12_FUNC(6)
667 | IPSR_8_FUNC(0)
668 | IPSR_4_FUNC(0)
669 | IPSR_0_FUNC(0));
670 pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
671 | IPSR_24_FUNC(0)
672 | IPSR_20_FUNC(0)
673 | IPSR_16_FUNC(0)
674 | IPSR_12_FUNC(0)
675 | IPSR_8_FUNC(6)
676 | IPSR_4_FUNC(6)
677 | IPSR_0_FUNC(6));
678 pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
679 | IPSR_24_FUNC(0)
680 | IPSR_20_FUNC(0)
681 | IPSR_16_FUNC(0)
682 | IPSR_12_FUNC(0)
683 | IPSR_8_FUNC(6)
684 | IPSR_4_FUNC(0)
685 | IPSR_0_FUNC(0));
686 pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6)
687 | IPSR_24_FUNC(6)
688 | IPSR_20_FUNC(6)
689 | IPSR_16_FUNC(6)
690 | IPSR_12_FUNC(6)
691 | IPSR_8_FUNC(0)
692 | IPSR_4_FUNC(0)
693 | IPSR_0_FUNC(0));
694 pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
695 | IPSR_24_FUNC(0)
696 | IPSR_20_FUNC(0)
697 | IPSR_16_FUNC(0)
698 | IPSR_8_FUNC(6)
699 | IPSR_4_FUNC(6)
700 | IPSR_0_FUNC(6));
701 pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1)
702 | IPSR_24_FUNC(1)
703 | IPSR_20_FUNC(1)
704 | IPSR_16_FUNC(1)
705 | IPSR_12_FUNC(0)
706 | IPSR_8_FUNC(0)
707 | IPSR_4_FUNC(0)
708 | IPSR_0_FUNC(0));
709 pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)
710 | IPSR_24_FUNC(0)
711 | IPSR_20_FUNC(0)
712 | IPSR_16_FUNC(0)
713 | IPSR_12_FUNC(0)
714 | IPSR_8_FUNC(0)
715 | IPSR_4_FUNC(0)
716 | IPSR_0_FUNC(0));
717 pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(1)
718 | IPSR_24_FUNC(0)
719 | IPSR_20_FUNC(0)
720 | IPSR_16_FUNC(0)
721 | IPSR_12_FUNC(0)
722 | IPSR_8_FUNC(0)
723 | IPSR_4_FUNC(0)
724 | IPSR_0_FUNC(0));
725 pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
726 | IPSR_24_FUNC(4)
727 | IPSR_20_FUNC(0)
728 | IPSR_16_FUNC(0)
729 | IPSR_12_FUNC(0)
730 | IPSR_8_FUNC(0)
731 | IPSR_4_FUNC(0)
732 | IPSR_0_FUNC(1));
733 pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
734 | IPSR_24_FUNC(0)
735 | IPSR_20_FUNC(0)
736 | IPSR_16_FUNC(0)
737 | IPSR_12_FUNC(0)
738 | IPSR_8_FUNC(4)
739 | IPSR_4_FUNC(0)
740 | IPSR_0_FUNC(0));
741 pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(8)
742 | IPSR_24_FUNC(0)
743 | IPSR_20_FUNC(0)
744 | IPSR_16_FUNC(0)
745 | IPSR_12_FUNC(0)
746 | IPSR_8_FUNC(3)
747 | IPSR_4_FUNC(0)
748 | IPSR_0_FUNC(0));
749 pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0)
750 | IPSR_24_FUNC(0)
751 | IPSR_20_FUNC(0)
752 | IPSR_16_FUNC(0)
753 | IPSR_12_FUNC(0)
754 | IPSR_8_FUNC(0)
755 | IPSR_4_FUNC(3)
756 | IPSR_0_FUNC(8));
757 pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)
758 | IPSR_24_FUNC(0)
759 | IPSR_20_FUNC(0)
760 | IPSR_16_FUNC(0)
761 | IPSR_12_FUNC(0)
762 | IPSR_8_FUNC(0)
763 | IPSR_4_FUNC(0)
764 | IPSR_0_FUNC(0));
765 pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0)
766 | IPSR_24_FUNC(0)
767 | IPSR_20_FUNC(0)
768 | IPSR_16_FUNC(0)
769 | IPSR_12_FUNC(0)
770 | IPSR_8_FUNC(0)
771 | IPSR_4_FUNC(0)
772 | IPSR_0_FUNC(0));
773 pfc_reg_write(PFC_IPSR17, IPSR_28_FUNC(0)
774 | IPSR_24_FUNC(0)
775 | IPSR_20_FUNC(0)
776 | IPSR_16_FUNC(0)
777 | IPSR_12_FUNC(0)
778 | IPSR_8_FUNC(0)
779 | IPSR_4_FUNC(1)
780 | IPSR_0_FUNC(0));
781 pfc_reg_write(PFC_IPSR18, IPSR_4_FUNC(0)
782 | IPSR_0_FUNC(0));
783
784 /* initialize GPIO/perihperal function select */
785 pfc_reg_write(PFC_GPSR0, GPSR0_D15
786 | GPSR0_D14
787 | GPSR0_D13
788 | GPSR0_D12
789 | GPSR0_D11
790 | GPSR0_D10
791 | GPSR0_D9
792 | GPSR0_D8);
793 pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
794 | GPSR1_EX_WAIT0_A
795 | GPSR1_A19
796 | GPSR1_A18
797 | GPSR1_A17
798 | GPSR1_A16
799 | GPSR1_A15
800 | GPSR1_A14
801 | GPSR1_A13
802 | GPSR1_A12
803 | GPSR1_A7
804 | GPSR1_A6
805 | GPSR1_A5
806 | GPSR1_A4
807 | GPSR1_A3
808 | GPSR1_A2
809 | GPSR1_A1
810 | GPSR1_A0);
811 pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
812 | GPSR2_AVB_AVTP_MATCH_A
813 | GPSR2_AVB_LINK
814 | GPSR2_AVB_PHY_INT
815 | GPSR2_AVB_MDC
816 | GPSR2_PWM2_A
817 | GPSR2_PWM1_A
818 | GPSR2_IRQ5
819 | GPSR2_IRQ4
820 | GPSR2_IRQ3
821 | GPSR2_IRQ2
822 | GPSR2_IRQ1
823 | GPSR2_IRQ0);
824 pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
825 | GPSR3_SD0_CD
826 | GPSR3_SD1_DAT3
827 | GPSR3_SD1_DAT2
828 | GPSR3_SD1_DAT1
829 | GPSR3_SD1_DAT0
830 | GPSR3_SD0_DAT3
831 | GPSR3_SD0_DAT2
832 | GPSR3_SD0_DAT1
833 | GPSR3_SD0_DAT0
834 | GPSR3_SD0_CMD
835 | GPSR3_SD0_CLK);
836 pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
837 | GPSR4_SD3_DAT6
838 | GPSR4_SD3_DAT3
839 | GPSR4_SD3_DAT2
840 | GPSR4_SD3_DAT1
841 | GPSR4_SD3_DAT0
842 | GPSR4_SD3_CMD
843 | GPSR4_SD3_CLK
844 | GPSR4_SD2_DS
845 | GPSR4_SD2_DAT3
846 | GPSR4_SD2_DAT2
847 | GPSR4_SD2_DAT1
848 | GPSR4_SD2_DAT0
849 | GPSR4_SD2_CMD
850 | GPSR4_SD2_CLK);
851 pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
852 | GPSR5_MSIOF0_SS1
853 | GPSR5_MSIOF0_SYNC
854 | GPSR5_HRTS0
855 | GPSR5_HCTS0
856 | GPSR5_HTX0
857 | GPSR5_HRX0
858 | GPSR5_HSCK0
859 | GPSR5_RX2_A
860 | GPSR5_TX2_A
861 | GPSR5_SCK2
862 | GPSR5_RTS1
863 | GPSR5_CTS1
864 | GPSR5_TX1_A
865 | GPSR5_RX1_A
866 | GPSR5_RTS0
867 | GPSR5_SCK0);
868 pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
869 | GPSR6_USB30_PWEN
870 | GPSR6_USB1_OVC
871 | GPSR6_USB1_PWEN
872 | GPSR6_USB0_OVC
873 | GPSR6_USB0_PWEN
874 | GPSR6_AUDIO_CLKB_B
875 | GPSR6_AUDIO_CLKA_A
876 | GPSR6_SSI_SDATA8
877 | GPSR6_SSI_SDATA7
878 | GPSR6_SSI_WS78
879 | GPSR6_SSI_SCK78
880 | GPSR6_SSI_WS6
881 | GPSR6_SSI_SCK6
882 | GPSR6_SSI_SDATA4
883 | GPSR6_SSI_WS4
884 | GPSR6_SSI_SCK4
885 | GPSR6_SSI_SDATA1_A
886 | GPSR6_SSI_SDATA0
887 | GPSR6_SSI_WS0129
888 | GPSR6_SSI_SCK0129);
889 pfc_reg_write(PFC_GPSR7, GPSR7_AVS2
890 | GPSR7_AVS1);
891
892 /* initialize POC control register */
893 pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
894 | POC_SD3_DAT7_33V
895 | POC_SD3_DAT6_33V
896 | POC_SD3_DAT5_33V
897 | POC_SD3_DAT4_33V
898 | POC_SD3_DAT3_33V
899 | POC_SD3_DAT2_33V
900 | POC_SD3_DAT1_33V
901 | POC_SD3_DAT0_33V
902 | POC_SD3_CMD_33V
903 | POC_SD3_CLK_33V
904 | POC_SD0_DAT3_33V
905 | POC_SD0_DAT2_33V
906 | POC_SD0_DAT1_33V
907 | POC_SD0_DAT0_33V
908 | POC_SD0_CMD_33V
909 | POC_SD0_CLK_33V);
910
911 /* initialize DRV control register */
912 reg = mmio_read_32(PFC_DRVCTRL0);
913 reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3)
914 | DRVCTRL0_QSPI0_MOSI_IO0(3)
915 | DRVCTRL0_QSPI0_MISO_IO1(3)
916 | DRVCTRL0_QSPI0_IO2(3)
917 | DRVCTRL0_QSPI0_IO3(3)
918 | DRVCTRL0_QSPI0_SSL(3)
919 | DRVCTRL0_QSPI1_SPCLK(3)
920 | DRVCTRL0_QSPI1_MOSI_IO0(3));
921 pfc_reg_write(PFC_DRVCTRL0, reg);
922 reg = mmio_read_32(PFC_DRVCTRL1);
923 reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3)
924 | DRVCTRL1_QSPI1_IO2(3)
925 | DRVCTRL1_QSPI1_IO3(3)
926 | DRVCTRL1_QSPI1_SS(3)
927 | DRVCTRL1_RPC_INT(3)
928 | DRVCTRL1_RPC_WP(3)
929 | DRVCTRL1_RPC_RESET(3)
930 | DRVCTRL1_AVB_RX_CTL(7));
931 pfc_reg_write(PFC_DRVCTRL1, reg);
932 reg = mmio_read_32(PFC_DRVCTRL2);
933 reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7)
934 | DRVCTRL2_AVB_RD0(7)
935 | DRVCTRL2_AVB_RD1(7)
936 | DRVCTRL2_AVB_RD2(7)
937 | DRVCTRL2_AVB_RD3(7)
938 | DRVCTRL2_AVB_TX_CTL(3)
939 | DRVCTRL2_AVB_TXC(3)
940 | DRVCTRL2_AVB_TD0(3));
941 pfc_reg_write(PFC_DRVCTRL2, reg);
942 reg = mmio_read_32(PFC_DRVCTRL3);
943 reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3)
944 | DRVCTRL3_AVB_TD2(3)
945 | DRVCTRL3_AVB_TD3(3)
946 | DRVCTRL3_AVB_TXCREFCLK(7)
947 | DRVCTRL3_AVB_MDIO(7)
948 | DRVCTRL3_AVB_MDC(7)
949 | DRVCTRL3_AVB_MAGIC(7)
950 | DRVCTRL3_AVB_PHY_INT(7));
951 pfc_reg_write(PFC_DRVCTRL3, reg);
952 reg = mmio_read_32(PFC_DRVCTRL4);
953 reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7)
954 | DRVCTRL4_AVB_AVTP_MATCH(7)
955 | DRVCTRL4_AVB_AVTP_CAPTURE(7)
956 | DRVCTRL4_IRQ0(7)
957 | DRVCTRL4_IRQ1(7)
958 | DRVCTRL4_IRQ2(7)
959 | DRVCTRL4_IRQ3(7)
960 | DRVCTRL4_IRQ4(7));
961 pfc_reg_write(PFC_DRVCTRL4, reg);
962 reg = mmio_read_32(PFC_DRVCTRL5);
963 reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7)
964 | DRVCTRL5_PWM0(7)
965 | DRVCTRL5_PWM1(7)
966 | DRVCTRL5_PWM2(7)
967 | DRVCTRL5_A0(3)
968 | DRVCTRL5_A1(3)
969 | DRVCTRL5_A2(3)
970 | DRVCTRL5_A3(3));
971 pfc_reg_write(PFC_DRVCTRL5, reg);
972 reg = mmio_read_32(PFC_DRVCTRL6);
973 reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3)
974 | DRVCTRL6_A5(3)
975 | DRVCTRL6_A6(3)
976 | DRVCTRL6_A7(3)
977 | DRVCTRL6_A8(7)
978 | DRVCTRL6_A9(7)
979 | DRVCTRL6_A10(7)
980 | DRVCTRL6_A11(7));
981 pfc_reg_write(PFC_DRVCTRL6, reg);
982 reg = mmio_read_32(PFC_DRVCTRL7);
983 reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3)
984 | DRVCTRL7_A13(3)
985 | DRVCTRL7_A14(3)
986 | DRVCTRL7_A15(3)
987 | DRVCTRL7_A16(3)
988 | DRVCTRL7_A17(3)
989 | DRVCTRL7_A18(3)
990 | DRVCTRL7_A19(3));
991 pfc_reg_write(PFC_DRVCTRL7, reg);
992 reg = mmio_read_32(PFC_DRVCTRL8);
993 reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7)
994 | DRVCTRL8_CS0(7)
995 | DRVCTRL8_CS1_A2(7)
996 | DRVCTRL8_BS(7)
997 | DRVCTRL8_RD(7)
998 | DRVCTRL8_RD_W(7)
999 | DRVCTRL8_WE0(7)
1000 | DRVCTRL8_WE1(7));
1001 pfc_reg_write(PFC_DRVCTRL8, reg);
1002 reg = mmio_read_32(PFC_DRVCTRL9);
1003 reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7)
1004 | DRVCTRL9_PRESETOU(7)
1005 | DRVCTRL9_D0(7)
1006 | DRVCTRL9_D1(7)
1007 | DRVCTRL9_D2(7)
1008 | DRVCTRL9_D3(7)
1009 | DRVCTRL9_D4(7)
1010 | DRVCTRL9_D5(7));
1011 pfc_reg_write(PFC_DRVCTRL9, reg);
1012 reg = mmio_read_32(PFC_DRVCTRL10);
1013 reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7)
1014 | DRVCTRL10_D7(7)
1015 | DRVCTRL10_D8(3)
1016 | DRVCTRL10_D9(3)
1017 | DRVCTRL10_D10(3)
1018 | DRVCTRL10_D11(3)
1019 | DRVCTRL10_D12(3)
1020 | DRVCTRL10_D13(3));
1021 pfc_reg_write(PFC_DRVCTRL10, reg);
1022 reg = mmio_read_32(PFC_DRVCTRL11);
1023 reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3)
1024 | DRVCTRL11_D15(3)
1025 | DRVCTRL11_AVS1(7)
1026 | DRVCTRL11_AVS2(7)
1027 | DRVCTRL11_GP7_02(7)
1028 | DRVCTRL11_GP7_03(7)
1029 | DRVCTRL11_DU_DOTCLKIN0(3)
1030 | DRVCTRL11_DU_DOTCLKIN1(3));
1031 pfc_reg_write(PFC_DRVCTRL11, reg);
1032 reg = mmio_read_32(PFC_DRVCTRL12);
1033 reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3)
1034 | DRVCTRL12_DU_DOTCLKIN3(3)
1035 | DRVCTRL12_DU_FSCLKST(3)
1036 | DRVCTRL12_DU_TMS(3));
1037 pfc_reg_write(PFC_DRVCTRL12, reg);
1038 reg = mmio_read_32(PFC_DRVCTRL13);
1039 reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3)
1040 | DRVCTRL13_ASEBRK(3)
1041 | DRVCTRL13_SD0_CLK(7)
1042 | DRVCTRL13_SD0_CMD(7)
1043 | DRVCTRL13_SD0_DAT0(7)
1044 | DRVCTRL13_SD0_DAT1(7)
1045 | DRVCTRL13_SD0_DAT2(7)
1046 | DRVCTRL13_SD0_DAT3(7));
1047 pfc_reg_write(PFC_DRVCTRL13, reg);
1048 reg = mmio_read_32(PFC_DRVCTRL14);
1049 reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7)
1050 | DRVCTRL14_SD1_CMD(7)
1051 | DRVCTRL14_SD1_DAT0(5)
1052 | DRVCTRL14_SD1_DAT1(5)
1053 | DRVCTRL14_SD1_DAT2(5)
1054 | DRVCTRL14_SD1_DAT3(5)
1055 | DRVCTRL14_SD2_CLK(5)
1056 | DRVCTRL14_SD2_CMD(5));
1057 pfc_reg_write(PFC_DRVCTRL14, reg);
1058 reg = mmio_read_32(PFC_DRVCTRL15);
1059 reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5)
1060 | DRVCTRL15_SD2_DAT1(5)
1061 | DRVCTRL15_SD2_DAT2(5)
1062 | DRVCTRL15_SD2_DAT3(5)
1063 | DRVCTRL15_SD2_DS(5)
1064 | DRVCTRL15_SD3_CLK(7)
1065 | DRVCTRL15_SD3_CMD(7)
1066 | DRVCTRL15_SD3_DAT0(7));
1067 pfc_reg_write(PFC_DRVCTRL15, reg);
1068 reg = mmio_read_32(PFC_DRVCTRL16);
1069 reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(7)
1070 | DRVCTRL16_SD3_DAT2(7)
1071 | DRVCTRL16_SD3_DAT3(7)
1072 | DRVCTRL16_SD3_DAT4(7)
1073 | DRVCTRL16_SD3_DAT5(7)
1074 | DRVCTRL16_SD3_DAT6(7)
1075 | DRVCTRL16_SD3_DAT7(7)
1076 | DRVCTRL16_SD3_DS(7));
1077 pfc_reg_write(PFC_DRVCTRL16, reg);
1078 reg = mmio_read_32(PFC_DRVCTRL17);
1079 reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7)
1080 | DRVCTRL17_SD0_WP(7)
1081 | DRVCTRL17_SD1_CD(7)
1082 | DRVCTRL17_SD1_WP(7)
1083 | DRVCTRL17_SCK0(7)
1084 | DRVCTRL17_RX0(7)
1085 | DRVCTRL17_TX0(7)
1086 | DRVCTRL17_CTS0(7));
1087 pfc_reg_write(PFC_DRVCTRL17, reg);
1088 reg = mmio_read_32(PFC_DRVCTRL18);
1089 reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7)
1090 | DRVCTRL18_RX1(7)
1091 | DRVCTRL18_TX1(7)
1092 | DRVCTRL18_CTS1(7)
1093 | DRVCTRL18_RTS1_TANS(7)
1094 | DRVCTRL18_SCK2(7)
1095 | DRVCTRL18_TX2(7)
1096 | DRVCTRL18_RX2(7));
1097 pfc_reg_write(PFC_DRVCTRL18, reg);
1098 reg = mmio_read_32(PFC_DRVCTRL19);
1099 reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7)
1100 | DRVCTRL19_HRX0(7)
1101 | DRVCTRL19_HTX0(7)
1102 | DRVCTRL19_HCTS0(7)
1103 | DRVCTRL19_HRTS0(7)
1104 | DRVCTRL19_MSIOF0_SCK(7)
1105 | DRVCTRL19_MSIOF0_SYNC(7)
1106 | DRVCTRL19_MSIOF0_SS1(7));
1107 pfc_reg_write(PFC_DRVCTRL19, reg);
1108 reg = mmio_read_32(PFC_DRVCTRL20);
1109 reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7)
1110 | DRVCTRL20_MSIOF0_SS2(7)
1111 | DRVCTRL20_MSIOF0_RXD(7)
1112 | DRVCTRL20_MLB_CLK(7)
1113 | DRVCTRL20_MLB_SIG(7)
1114 | DRVCTRL20_MLB_DAT(7)
1115 | DRVCTRL20_MLB_REF(7)
1116 | DRVCTRL20_SSI_SCK0129(7));
1117 pfc_reg_write(PFC_DRVCTRL20, reg);
1118 reg = mmio_read_32(PFC_DRVCTRL21);
1119 reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7)
1120 | DRVCTRL21_SSI_SDATA0(7)
1121 | DRVCTRL21_SSI_SDATA1(7)
1122 | DRVCTRL21_SSI_SDATA2(7)
1123 | DRVCTRL21_SSI_SCK34(7)
1124 | DRVCTRL21_SSI_WS34(7)
1125 | DRVCTRL21_SSI_SDATA3(7)
1126 | DRVCTRL21_SSI_SCK4(7));
1127 pfc_reg_write(PFC_DRVCTRL21, reg);
1128 reg = mmio_read_32(PFC_DRVCTRL22);
1129 reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7)
1130 | DRVCTRL22_SSI_SDATA4(7)
1131 | DRVCTRL22_SSI_SCK5(7)
1132 | DRVCTRL22_SSI_WS5(7)
1133 | DRVCTRL22_SSI_SDATA5(7)
1134 | DRVCTRL22_SSI_SCK6(7)
1135 | DRVCTRL22_SSI_WS6(7)
1136 | DRVCTRL22_SSI_SDATA6(7));
1137 pfc_reg_write(PFC_DRVCTRL22, reg);
1138 reg = mmio_read_32(PFC_DRVCTRL23);
1139 reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7)
1140 | DRVCTRL23_SSI_WS78(7)
1141 | DRVCTRL23_SSI_SDATA7(7)
1142 | DRVCTRL23_SSI_SDATA8(7)
1143 | DRVCTRL23_SSI_SDATA9(7)
1144 | DRVCTRL23_AUDIO_CLKA(7)
1145 | DRVCTRL23_AUDIO_CLKB(7)
1146 | DRVCTRL23_USB0_PWEN(7));
1147 pfc_reg_write(PFC_DRVCTRL23, reg);
1148 reg = mmio_read_32(PFC_DRVCTRL24);
1149 reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7)
1150 | DRVCTRL24_USB1_PWEN(7)
1151 | DRVCTRL24_USB1_OVC(7)
1152 | DRVCTRL24_USB30_PWEN(7)
1153 | DRVCTRL24_USB30_OVC(7)
1154 | DRVCTRL24_USB31_PWEN(7)
1155 | DRVCTRL24_USB31_OVC(7));
1156 pfc_reg_write(PFC_DRVCTRL24, reg);
1157
1158 /* initialize LSI pin pull-up/down control */
1159 pfc_reg_write(PFC_PUD0, 0x00005FBFU);
1160 pfc_reg_write(PFC_PUD1, 0x00300FFEU);
1161 pfc_reg_write(PFC_PUD2, 0x330001E6U);
1162 pfc_reg_write(PFC_PUD3, 0x000002E0U);
1163 pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
1164 pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
1165 pfc_reg_write(PFC_PUD6, 0x00000055U);
1166
1167 /* initialize LSI pin pull-enable register */
1168 pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
1169 pfc_reg_write(PFC_PUEN1, 0x00100234U);
1170 pfc_reg_write(PFC_PUEN2, 0x000004C4U);
1171 pfc_reg_write(PFC_PUEN3, 0x00000200U);
1172 pfc_reg_write(PFC_PUEN4, 0x3E000000U);
1173 pfc_reg_write(PFC_PUEN5, 0x1F000805U);
1174 pfc_reg_write(PFC_PUEN6, 0x00000006U);
1175
1176 /* initialize positive/negative logic select */
1177 mmio_write_32(GPIO_POSNEG0, 0x00000000U);
1178 mmio_write_32(GPIO_POSNEG1, 0x00000000U);
1179 mmio_write_32(GPIO_POSNEG2, 0x00000000U);
1180 mmio_write_32(GPIO_POSNEG3, 0x00000000U);
1181 mmio_write_32(GPIO_POSNEG4, 0x00000000U);
1182 mmio_write_32(GPIO_POSNEG5, 0x00000000U);
1183 mmio_write_32(GPIO_POSNEG6, 0x00000000U);
1184 mmio_write_32(GPIO_POSNEG7, 0x00000000U);
1185
1186 /* initialize general IO/interrupt switching */
1187 mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
1188 mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
1189 mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
1190 mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
1191 mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
1192 mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
1193 mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
1194 mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
1195
1196 /* initialize general output register */
1197 mmio_write_32(GPIO_OUTDT1, 0x00000000U);
1198 mmio_write_32(GPIO_OUTDT2, 0x00000400U);
1199 mmio_write_32(GPIO_OUTDT3, 0x0000C000U);
1200 mmio_write_32(GPIO_OUTDT5, 0x00000006U);
1201 mmio_write_32(GPIO_OUTDT6, 0x00003880U);
1202
1203 /* initialize general input/output switching */
1204 mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
1205 mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U);
1206 mmio_write_32(GPIO_INOUTSEL2, 0x00000400U);
1207 mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U);
1208 mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
1209 #if (RCAR_GEN3_ULCB == 1)
1210 mmio_write_32(GPIO_INOUTSEL5, 0x0000000EU);
1211 #else
1212 mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
1213 #endif
1214 mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
1215 mmio_write_32(GPIO_INOUTSEL7, 0x00000000U);
1216 }
1217