1 /*
2 * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <string.h>
9
10 #include <arch.h>
11 #include <arch_helpers.h>
12 #include <common/debug.h>
13 #include <lib/bakery_lock.h>
14 #include <lib/mmio.h>
15 #include <lib/xlat_tables/xlat_tables_v2.h>
16 #include <plat/common/platform.h>
17
18 #include "iic_dvfs.h"
19 #include "rcar_def.h"
20 #include "rcar_private.h"
21 #include "micro_delay.h"
22 #include "pwrc.h"
23
24 /*
25 * Someday there will be a generic power controller api. At the moment each
26 * platform has its own pwrc so just exporting functions should be acceptable.
27 */
28 RCAR_INSTANTIATE_LOCK
29
30 #define WUP_IRQ_SHIFT (0U)
31 #define WUP_FIQ_SHIFT (8U)
32 #define WUP_CSD_SHIFT (16U)
33 #define BIT_SOFTRESET (1U<<15)
34 #define BIT_CA53_SCU (1U<<21)
35 #define BIT_CA57_SCU (1U<<12)
36 #define REQ_RESUME (1U<<1)
37 #define REQ_OFF (1U<<0)
38 #define STATUS_PWRUP (1U<<4)
39 #define STATUS_PWRDOWN (1U<<0)
40 #define STATE_CA57_CPU (27U)
41 #define STATE_CA53_CPU (22U)
42 #define MODE_L2_DOWN (0x00000002U)
43 #define CPU_PWR_OFF (0x00000003U)
44 #define RCAR_PSTR_MASK (0x00000003U)
45 #define ST_ALL_STANDBY (0x00003333U)
46 /* Suspend to ram */
47 #define DBSC4_REG_BASE (0xE6790000U)
48 #define DBSC4_REG_DBSYSCNT0 (DBSC4_REG_BASE + 0x0100U)
49 #define DBSC4_REG_DBACEN (DBSC4_REG_BASE + 0x0200U)
50 #define DBSC4_REG_DBCMD (DBSC4_REG_BASE + 0x0208U)
51 #define DBSC4_REG_DBRFEN (DBSC4_REG_BASE + 0x0204U)
52 #define DBSC4_REG_DBWAIT (DBSC4_REG_BASE + 0x0210U)
53 #define DBSC4_REG_DBCALCNF (DBSC4_REG_BASE + 0x0424U)
54 #define DBSC4_REG_DBDFIPMSTRCNF (DBSC4_REG_BASE + 0x0520U)
55 #define DBSC4_REG_DBPDLK0 (DBSC4_REG_BASE + 0x0620U)
56 #define DBSC4_REG_DBPDRGA0 (DBSC4_REG_BASE + 0x0624U)
57 #define DBSC4_REG_DBPDRGD0 (DBSC4_REG_BASE + 0x0628U)
58 #define DBSC4_REG_DBCAM0CTRL0 (DBSC4_REG_BASE + 0x0940U)
59 #define DBSC4_REG_DBCAM0STAT0 (DBSC4_REG_BASE + 0x0980U)
60 #define DBSC4_REG_DBCAM1STAT0 (DBSC4_REG_BASE + 0x0990U)
61 #define DBSC4_REG_DBCAM2STAT0 (DBSC4_REG_BASE + 0x09A0U)
62 #define DBSC4_REG_DBCAM3STAT0 (DBSC4_REG_BASE + 0x09B0U)
63 #define DBSC4_BIT_DBACEN_ACCEN ((uint32_t)(1U << 0))
64 #define DBSC4_BIT_DBRFEN_ARFEN ((uint32_t)(1U << 0))
65 #define DBSC4_BIT_DBCAMxSTAT0 (0x00000001U)
66 #define DBSC4_BIT_DBDFIPMSTRCNF_PMSTREN (0x00000001U)
67 #define DBSC4_SET_DBCMD_OPC_PRE (0x04000000U)
68 #define DBSC4_SET_DBCMD_OPC_SR (0x0A000000U)
69 #define DBSC4_SET_DBCMD_OPC_PD (0x08000000U)
70 #define DBSC4_SET_DBCMD_OPC_MRW (0x0E000000U)
71 #define DBSC4_SET_DBCMD_CH_ALL (0x00800000U)
72 #define DBSC4_SET_DBCMD_RANK_ALL (0x00040000U)
73 #define DBSC4_SET_DBCMD_ARG_ALL (0x00000010U)
74 #define DBSC4_SET_DBCMD_ARG_ENTER (0x00000000U)
75 #define DBSC4_SET_DBCMD_ARG_MRW_ODTC (0x00000B00U)
76 #define DBSC4_SET_DBSYSCNT0_WRITE_ENABLE (0x00001234U)
77 #define DBSC4_SET_DBSYSCNT0_WRITE_DISABLE (0x00000000U)
78 #define DBSC4_SET_DBPDLK0_PHY_ACCESS (0x0000A55AU)
79 #define DBSC4_SET_DBPDRGA0_ACIOCR0 (0x0000001AU)
80 #define DBSC4_SET_DBPDRGD0_ACIOCR0 (0x33C03C11U)
81 #define DBSC4_SET_DBPDRGA0_DXCCR (0x00000020U)
82 #define DBSC4_SET_DBPDRGD0_DXCCR (0x00181006U)
83 #define DBSC4_SET_DBPDRGA0_PGCR1 (0x00000003U)
84 #define DBSC4_SET_DBPDRGD0_PGCR1 (0x0380C600U)
85 #define DBSC4_SET_DBPDRGA0_ACIOCR1 (0x0000001BU)
86 #define DBSC4_SET_DBPDRGD0_ACIOCR1 (0xAAAAAAAAU)
87 #define DBSC4_SET_DBPDRGA0_ACIOCR3 (0x0000001DU)
88 #define DBSC4_SET_DBPDRGD0_ACIOCR3 (0xAAAAAAAAU)
89 #define DBSC4_SET_DBPDRGA0_ACIOCR5 (0x0000001FU)
90 #define DBSC4_SET_DBPDRGD0_ACIOCR5 (0x000000AAU)
91 #define DBSC4_SET_DBPDRGA0_DX0GCR2 (0x000000A2U)
92 #define DBSC4_SET_DBPDRGD0_DX0GCR2 (0xAAAA0000U)
93 #define DBSC4_SET_DBPDRGA0_DX1GCR2 (0x000000C2U)
94 #define DBSC4_SET_DBPDRGD0_DX1GCR2 (0xAAAA0000U)
95 #define DBSC4_SET_DBPDRGA0_DX2GCR2 (0x000000E2U)
96 #define DBSC4_SET_DBPDRGD0_DX2GCR2 (0xAAAA0000U)
97 #define DBSC4_SET_DBPDRGA0_DX3GCR2 (0x00000102U)
98 #define DBSC4_SET_DBPDRGD0_DX3GCR2 (0xAAAA0000U)
99 #define DBSC4_SET_DBPDRGA0_ZQCR (0x00000090U)
100 #define DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 (0x04058904U)
101 #define DBSC4_SET_DBPDRGD0_ZQCR_MD19_1 (0x04058A04U)
102 #define DBSC4_SET_DBPDRGA0_DX0GCR0 (0x000000A0U)
103 #define DBSC4_SET_DBPDRGD0_DX0GCR0 (0x7C0002E5U)
104 #define DBSC4_SET_DBPDRGA0_DX1GCR0 (0x000000C0U)
105 #define DBSC4_SET_DBPDRGD0_DX1GCR0 (0x7C0002E5U)
106 #define DBSC4_SET_DBPDRGA0_DX2GCR0 (0x000000E0U)
107 #define DBSC4_SET_DBPDRGD0_DX2GCR0 (0x7C0002E5U)
108 #define DBSC4_SET_DBPDRGA0_DX3GCR0 (0x00000100U)
109 #define DBSC4_SET_DBPDRGD0_DX3GCR0 (0x7C0002E5U)
110 #define DBSC4_SET_DBPDRGA0_DX0GCR1 (0x000000A1U)
111 #define DBSC4_SET_DBPDRGD0_DX0GCR1 (0x55550000U)
112 #define DBSC4_SET_DBPDRGA0_DX1GCR1 (0x000000C1U)
113 #define DBSC4_SET_DBPDRGD0_DX1GCR1 (0x55550000U)
114 #define DBSC4_SET_DBPDRGA0_DX2GCR1 (0x000000E1U)
115 #define DBSC4_SET_DBPDRGD0_DX2GCR1 (0x55550000U)
116 #define DBSC4_SET_DBPDRGA0_DX3GCR1 (0x00000101U)
117 #define DBSC4_SET_DBPDRGD0_DX3GCR1 (0x55550000U)
118 #define DBSC4_SET_DBPDRGA0_DX0GCR3 (0x000000A3U)
119 #define DBSC4_SET_DBPDRGD0_DX0GCR3 (0x00008484U)
120 #define DBSC4_SET_DBPDRGA0_DX1GCR3 (0x000000C3U)
121 #define DBSC4_SET_DBPDRGD0_DX1GCR3 (0x00008484U)
122 #define DBSC4_SET_DBPDRGA0_DX2GCR3 (0x000000E3U)
123 #define DBSC4_SET_DBPDRGD0_DX2GCR3 (0x00008484U)
124 #define DBSC4_SET_DBPDRGA0_DX3GCR3 (0x00000103U)
125 #define DBSC4_SET_DBPDRGD0_DX3GCR3 (0x00008484U)
126 #define RST_BASE (0xE6160000U)
127 #define RST_MODEMR (RST_BASE + 0x0060U)
128 #define RST_MODEMR_BIT0 (0x00000001U)
129
130 #define RCAR_CNTCR_OFF (0x00U)
131 #define RCAR_CNTCVL_OFF (0x08U)
132 #define RCAR_CNTCVU_OFF (0x0CU)
133 #define RCAR_CNTFID_OFF (0x20U)
134
135 #define RCAR_CNTCR_EN ((uint32_t)1U << 0U)
136 #define RCAR_CNTCR_FCREQ(x) ((uint32_t)(x) << 8U)
137
138 #if PMIC_ROHM_BD9571
139 #define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4))
140 #define PMIC_BKUP_MODE_CNT (0x20U)
141 #define PMIC_QLLM_CNT (0x27U)
142 #define PMIC_RETRY_MAX (100U)
143 #endif
144 #define SCTLR_EL3_M_BIT ((uint32_t)1U << 0)
145 #define RCAR_CA53CPU_NUM_MAX (4U)
146 #define RCAR_CA57CPU_NUM_MAX (4U)
147 #define IS_A53A57(c) ((c) == RCAR_CLUSTER_A53A57)
148 #define IS_CA57(c) ((c) == RCAR_CLUSTER_CA57)
149 #define IS_CA53(c) ((c) == RCAR_CLUSTER_CA53)
150
151 #ifndef __ASSEMBLER__
152 IMPORT_SYM(unsigned long, __system_ram_start__, SYSTEM_RAM_START);
153 IMPORT_SYM(unsigned long, __system_ram_end__, SYSTEM_RAM_END);
154 IMPORT_SYM(unsigned long, __SRAM_COPY_START__, SRAM_COPY_START);
155 #endif
156
rcar_pwrc_status(uint64_t mpidr)157 uint32_t rcar_pwrc_status(uint64_t mpidr)
158 {
159 uint32_t ret = 0;
160 uint64_t cm, cpu;
161 uint32_t reg;
162 uint32_t c;
163
164 rcar_lock_get();
165
166 c = rcar_pwrc_get_cluster();
167 cm = mpidr & MPIDR_CLUSTER_MASK;
168
169 if (!IS_A53A57(c) && cm != 0) {
170 ret = RCAR_INVALID;
171 goto done;
172 }
173
174 reg = mmio_read_32(RCAR_PRR);
175 cpu = mpidr & MPIDR_CPU_MASK;
176
177 if (IS_CA53(c))
178 if (reg & (1 << (STATE_CA53_CPU + cpu)))
179 ret = RCAR_INVALID;
180 if (IS_CA57(c))
181 if (reg & (1 << (STATE_CA57_CPU + cpu)))
182 ret = RCAR_INVALID;
183 done:
184 rcar_lock_release();
185
186 return ret;
187 }
188
scu_power_up(uint64_t mpidr)189 static void scu_power_up(uint64_t mpidr)
190 {
191 uintptr_t reg_pwrsr, reg_cpumcr, reg_pwron, reg_pwrer;
192 uint32_t c, sysc_reg_bit;
193
194 c = rcar_pwrc_get_mpidr_cluster(mpidr);
195 reg_cpumcr = IS_CA57(c) ? RCAR_CA57CPUCMCR : RCAR_CA53CPUCMCR;
196 sysc_reg_bit = IS_CA57(c) ? BIT_CA57_SCU : BIT_CA53_SCU;
197 reg_pwron = IS_CA57(c) ? RCAR_PWRONCR5 : RCAR_PWRONCR3;
198 reg_pwrer = IS_CA57(c) ? RCAR_PWRER5 : RCAR_PWRER3;
199 reg_pwrsr = IS_CA57(c) ? RCAR_PWRSR5 : RCAR_PWRSR3;
200
201 if ((mmio_read_32(reg_pwrsr) & STATUS_PWRDOWN) == 0)
202 return;
203
204 if (mmio_read_32(reg_cpumcr) != 0)
205 mmio_write_32(reg_cpumcr, 0);
206
207 mmio_setbits_32(RCAR_SYSCIER, sysc_reg_bit);
208 mmio_setbits_32(RCAR_SYSCIMR, sysc_reg_bit);
209
210 do {
211 while ((mmio_read_32(RCAR_SYSCSR) & REQ_RESUME) == 0)
212 ;
213 mmio_write_32(reg_pwron, 1);
214 } while (mmio_read_32(reg_pwrer) & 1);
215
216 while ((mmio_read_32(RCAR_SYSCISR) & sysc_reg_bit) == 0)
217 ;
218 mmio_write_32(RCAR_SYSCISR, sysc_reg_bit);
219 while ((mmio_read_32(reg_pwrsr) & STATUS_PWRUP) == 0)
220 ;
221 }
222
rcar_pwrc_cpuon(uint64_t mpidr)223 void rcar_pwrc_cpuon(uint64_t mpidr)
224 {
225 uint32_t res_data, on_data;
226 uintptr_t res_reg, on_reg;
227 uint32_t limit, c;
228 uint64_t cpu;
229
230 rcar_lock_get();
231
232 c = rcar_pwrc_get_mpidr_cluster(mpidr);
233 res_reg = IS_CA53(c) ? RCAR_CA53RESCNT : RCAR_CA57RESCNT;
234 on_reg = IS_CA53(c) ? RCAR_CA53WUPCR : RCAR_CA57WUPCR;
235 limit = IS_CA53(c) ? 0x5A5A0000 : 0xA5A50000;
236
237 res_data = mmio_read_32(res_reg) | limit;
238 scu_power_up(mpidr);
239 cpu = mpidr & MPIDR_CPU_MASK;
240 on_data = 1 << cpu;
241 mmio_write_32(RCAR_CPGWPR, ~on_data);
242 mmio_write_32(on_reg, on_data);
243 mmio_write_32(res_reg, res_data & (~(1 << (3 - cpu))));
244
245 rcar_lock_release();
246 }
247
rcar_pwrc_cpuoff(uint64_t mpidr)248 void rcar_pwrc_cpuoff(uint64_t mpidr)
249 {
250 uint32_t c;
251 uintptr_t reg;
252 uint64_t cpu;
253
254 rcar_lock_get();
255
256 cpu = mpidr & MPIDR_CPU_MASK;
257 c = rcar_pwrc_get_mpidr_cluster(mpidr);
258 reg = IS_CA53(c) ? RCAR_CA53CPU0CR : RCAR_CA57CPU0CR;
259
260 if (read_mpidr_el1() != mpidr)
261 panic();
262
263 mmio_write_32(RCAR_CPGWPR, ~CPU_PWR_OFF);
264 mmio_write_32(reg + cpu * 0x0010, CPU_PWR_OFF);
265
266 rcar_lock_release();
267 }
268
rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr)269 void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr)
270 {
271 uint32_t c, shift_irq, shift_fiq;
272 uintptr_t reg;
273 uint64_t cpu;
274
275 rcar_lock_get();
276
277 cpu = mpidr & MPIDR_CPU_MASK;
278 c = rcar_pwrc_get_mpidr_cluster(mpidr);
279 reg = IS_CA53(c) ? RCAR_WUPMSKCA53 : RCAR_WUPMSKCA57;
280
281 shift_irq = WUP_IRQ_SHIFT + cpu;
282 shift_fiq = WUP_FIQ_SHIFT + cpu;
283
284 mmio_write_32(reg, ~((uint32_t) 1 << shift_irq) &
285 ~((uint32_t) 1 << shift_fiq));
286 rcar_lock_release();
287 }
288
rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr)289 void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr)
290 {
291 uint32_t c, shift_irq, shift_fiq;
292 uintptr_t reg;
293 uint64_t cpu;
294
295 rcar_lock_get();
296
297 cpu = mpidr & MPIDR_CPU_MASK;
298 c = rcar_pwrc_get_mpidr_cluster(mpidr);
299 reg = IS_CA53(c) ? RCAR_WUPMSKCA53 : RCAR_WUPMSKCA57;
300
301 shift_irq = WUP_IRQ_SHIFT + cpu;
302 shift_fiq = WUP_FIQ_SHIFT + cpu;
303
304 mmio_write_32(reg, ((uint32_t) 1 << shift_irq) |
305 ((uint32_t) 1 << shift_fiq));
306 rcar_lock_release();
307 }
308
rcar_pwrc_clusteroff(uint64_t mpidr)309 void rcar_pwrc_clusteroff(uint64_t mpidr)
310 {
311 uint32_t c, product, cut, reg;
312 uintptr_t dst;
313
314 rcar_lock_get();
315
316 reg = mmio_read_32(RCAR_PRR);
317 product = reg & PRR_PRODUCT_MASK;
318 cut = reg & PRR_CUT_MASK;
319
320 c = rcar_pwrc_get_mpidr_cluster(mpidr);
321 dst = IS_CA53(c) ? RCAR_CA53CPUCMCR : RCAR_CA57CPUCMCR;
322
323 if (PRR_PRODUCT_M3 == product && cut < PRR_PRODUCT_30)
324 goto done;
325
326 if (PRR_PRODUCT_H3 == product && cut <= PRR_PRODUCT_20)
327 goto done;
328
329 /* all of the CPUs in the cluster is in the CoreStandby mode */
330 mmio_write_32(dst, MODE_L2_DOWN);
331 done:
332 rcar_lock_release();
333 }
334
335 static uint64_t rcar_pwrc_saved_cntpct_el0;
336 static uint32_t rcar_pwrc_saved_cntfid;
337
338 #if RCAR_SYSTEM_SUSPEND
rcar_pwrc_save_timer_state(void)339 static void rcar_pwrc_save_timer_state(void)
340 {
341 rcar_pwrc_saved_cntpct_el0 = read_cntpct_el0();
342
343 rcar_pwrc_saved_cntfid =
344 mmio_read_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTFID_OFF));
345 }
346 #endif
347
rcar_pwrc_restore_timer_state(void)348 void rcar_pwrc_restore_timer_state(void)
349 {
350 /* Stop timer before restoring counter value */
351 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCR_OFF), 0U);
352
353 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCVL_OFF),
354 (uint32_t)(rcar_pwrc_saved_cntpct_el0 & 0xFFFFFFFFU));
355 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCVU_OFF),
356 (uint32_t)(rcar_pwrc_saved_cntpct_el0 >> 32U));
357
358 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTFID_OFF),
359 rcar_pwrc_saved_cntfid);
360
361 /* Start generic timer back */
362 write_cntfrq_el0((u_register_t)plat_get_syscnt_freq2());
363
364 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCR_OFF),
365 (RCAR_CNTCR_FCREQ(0U) | RCAR_CNTCR_EN));
366 }
367
368 #if !PMIC_ROHM_BD9571
rcar_pwrc_system_reset(void)369 void rcar_pwrc_system_reset(void)
370 {
371 mmio_write_32(RCAR_SRESCR, 0x5AA50000U | BIT_SOFTRESET);
372 }
373 #endif /* PMIC_ROHM_BD9571 */
374
375 #define RST_CA53_CPU0_BARH (0xE6160080U)
376 #define RST_CA53_CPU0_BARL (0xE6160084U)
377 #define RST_CA57_CPU0_BARH (0xE61600C0U)
378 #define RST_CA57_CPU0_BARL (0xE61600C4U)
379
rcar_pwrc_setup(void)380 void rcar_pwrc_setup(void)
381 {
382 uintptr_t rst_barh;
383 uintptr_t rst_barl;
384 uint32_t i, j;
385 uint64_t reset = (uint64_t) (&plat_secondary_reset) & 0xFFFFFFFF;
386
387 const uint32_t cluster[PLATFORM_CLUSTER_COUNT] = {
388 RCAR_CLUSTER_CA53,
389 RCAR_CLUSTER_CA57
390 };
391 const uintptr_t reg_barh[PLATFORM_CLUSTER_COUNT] = {
392 RST_CA53_CPU0_BARH,
393 RST_CA57_CPU0_BARH
394 };
395 const uintptr_t reg_barl[PLATFORM_CLUSTER_COUNT] = {
396 RST_CA53_CPU0_BARL,
397 RST_CA57_CPU0_BARL
398 };
399
400 for (i = 0; i < PLATFORM_CLUSTER_COUNT; i++) {
401 rst_barh = reg_barh[i];
402 rst_barl = reg_barl[i];
403 for (j = 0; j < rcar_pwrc_get_cpu_num(cluster[i]); j++) {
404 mmio_write_32(rst_barh, 0);
405 mmio_write_32(rst_barl, (uint32_t) reset);
406 rst_barh += 0x10;
407 rst_barl += 0x10;
408 }
409 }
410
411 rcar_lock_init();
412 }
413
414 #if RCAR_SYSTEM_SUSPEND
415 #define DBCAM_FLUSH(__bit) \
416 do { \
417 ; \
418 } while (!(mmio_read_32(DBSC4_REG_DBCAM##__bit##STAT0) & DBSC4_BIT_DBCAMxSTAT0))
419
420
421 static void __attribute__ ((section(".system_ram")))
rcar_pwrc_set_self_refresh(void)422 rcar_pwrc_set_self_refresh(void)
423 {
424 uint32_t reg = mmio_read_32(RCAR_PRR);
425 uint32_t cut, product;
426
427 product = reg & PRR_PRODUCT_MASK;
428 cut = reg & PRR_CUT_MASK;
429
430 if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30)
431 goto self_refresh;
432
433 if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
434 goto self_refresh;
435
436 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
437
438 self_refresh:
439
440 /* DFI_PHYMSTR_ACK setting */
441 mmio_write_32(DBSC4_REG_DBDFIPMSTRCNF,
442 mmio_read_32(DBSC4_REG_DBDFIPMSTRCNF) &
443 (~DBSC4_BIT_DBDFIPMSTRCNF_PMSTREN));
444
445 /* Set the Self-Refresh mode */
446 mmio_write_32(DBSC4_REG_DBACEN, 0);
447
448 if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
449 rcar_micro_delay(100);
450 else if (product == PRR_PRODUCT_H3) {
451 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
452 DBCAM_FLUSH(0);
453 DBCAM_FLUSH(1);
454 DBCAM_FLUSH(2);
455 DBCAM_FLUSH(3);
456 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
457 } else if (product == PRR_PRODUCT_M3) {
458 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
459 DBCAM_FLUSH(0);
460 DBCAM_FLUSH(1);
461 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
462 } else {
463 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
464 DBCAM_FLUSH(0);
465 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
466 }
467
468 /* Set the SDRAM calibration configuration register */
469 mmio_write_32(DBSC4_REG_DBCALCNF, 0);
470
471 reg = DBSC4_SET_DBCMD_OPC_PRE | DBSC4_SET_DBCMD_CH_ALL |
472 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ALL;
473 mmio_write_32(DBSC4_REG_DBCMD, reg);
474 while (mmio_read_32(DBSC4_REG_DBWAIT))
475 ;
476
477 /* Self-Refresh entry command */
478 reg = DBSC4_SET_DBCMD_OPC_SR | DBSC4_SET_DBCMD_CH_ALL |
479 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER;
480 mmio_write_32(DBSC4_REG_DBCMD, reg);
481 while (mmio_read_32(DBSC4_REG_DBWAIT))
482 ;
483
484 /* Mode Register Write command. (ODT disabled) */
485 reg = DBSC4_SET_DBCMD_OPC_MRW | DBSC4_SET_DBCMD_CH_ALL |
486 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_MRW_ODTC;
487 mmio_write_32(DBSC4_REG_DBCMD, reg);
488 while (mmio_read_32(DBSC4_REG_DBWAIT))
489 ;
490
491 /* Power Down entry command */
492 reg = DBSC4_SET_DBCMD_OPC_PD | DBSC4_SET_DBCMD_CH_ALL |
493 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER;
494 mmio_write_32(DBSC4_REG_DBCMD, reg);
495 while (mmio_read_32(DBSC4_REG_DBWAIT))
496 ;
497
498 /* Set the auto-refresh enable register */
499 mmio_write_32(DBSC4_REG_DBRFEN, 0U);
500 rcar_micro_delay(1U);
501
502 if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30)
503 return;
504
505 if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
506 return;
507
508 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE);
509 }
510
511 static void __attribute__ ((section(".system_ram")))
rcar_pwrc_set_self_refresh_e3(void)512 rcar_pwrc_set_self_refresh_e3(void)
513 {
514 uint32_t ddr_md;
515 uint32_t reg;
516
517 ddr_md = (mmio_read_32(RST_MODEMR) >> 19) & RST_MODEMR_BIT0;
518
519 /* Write enable */
520 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
521 mmio_write_32(DBSC4_REG_DBACEN, 0);
522 DBCAM_FLUSH(0);
523
524 reg = DBSC4_SET_DBCMD_OPC_PRE | DBSC4_SET_DBCMD_CH_ALL |
525 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ALL;
526 mmio_write_32(DBSC4_REG_DBCMD, reg);
527 while (mmio_read_32(DBSC4_REG_DBWAIT))
528 ;
529
530 reg = DBSC4_SET_DBCMD_OPC_SR | DBSC4_SET_DBCMD_CH_ALL |
531 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER;
532 mmio_write_32(DBSC4_REG_DBCMD, reg);
533 while (mmio_read_32(DBSC4_REG_DBWAIT))
534 ;
535
536 /* Set the auto-refresh enable register */
537 /* Set the ARFEN bit to 0 in the DBRFEN */
538 mmio_write_32(DBSC4_REG_DBRFEN, 0);
539
540 mmio_write_32(DBSC4_REG_DBPDLK0, DBSC4_SET_DBPDLK0_PHY_ACCESS);
541
542 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR0);
543 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR0);
544
545 /* DDR_DXCCR */
546 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DXCCR);
547 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DXCCR);
548
549 /* DDR_PGCR1 */
550 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_PGCR1);
551 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_PGCR1);
552
553 /* DDR_ACIOCR1 */
554 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR1);
555 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR1);
556
557 /* DDR_ACIOCR3 */
558 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR3);
559 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR3);
560
561 /* DDR_ACIOCR5 */
562 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR5);
563 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR5);
564
565 /* DDR_DX0GCR2 */
566 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR2);
567 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR2);
568
569 /* DDR_DX1GCR2 */
570 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR2);
571 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR2);
572
573 /* DDR_DX2GCR2 */
574 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR2);
575 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR2);
576
577 /* DDR_DX3GCR2 */
578 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR2);
579 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR2);
580
581 /* DDR_ZQCR */
582 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ZQCR);
583
584 mmio_write_32(DBSC4_REG_DBPDRGD0, ddr_md == 0 ?
585 DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 :
586 DBSC4_SET_DBPDRGD0_ZQCR_MD19_1);
587
588 /* DDR_DX0GCR0 */
589 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR0);
590 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR0);
591
592 /* DDR_DX1GCR0 */
593 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR0);
594 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR0);
595
596 /* DDR_DX2GCR0 */
597 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR0);
598 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR0);
599
600 /* DDR_DX3GCR0 */
601 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR0);
602 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR0);
603
604 /* DDR_DX0GCR1 */
605 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR1);
606 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR1);
607
608 /* DDR_DX1GCR1 */
609 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR1);
610 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR1);
611
612 /* DDR_DX2GCR1 */
613 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR1);
614 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR1);
615
616 /* DDR_DX3GCR1 */
617 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR1);
618 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR1);
619
620 /* DDR_DX0GCR3 */
621 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR3);
622 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR3);
623
624 /* DDR_DX1GCR3 */
625 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR3);
626 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR3);
627
628 /* DDR_DX2GCR3 */
629 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR3);
630 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR3);
631
632 /* DDR_DX3GCR3 */
633 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR3);
634 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR3);
635
636 /* Write disable */
637 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE);
638 }
639
640 void __attribute__ ((section(".system_ram"))) __attribute__ ((noinline))
rcar_pwrc_go_suspend_to_ram(void)641 rcar_pwrc_go_suspend_to_ram(void)
642 {
643 #if PMIC_ROHM_BD9571
644 int32_t rc = -1, qllm = -1;
645 uint8_t mode;
646 uint32_t i;
647 #endif
648 uint32_t reg, product;
649
650 reg = mmio_read_32(RCAR_PRR);
651 product = reg & PRR_PRODUCT_MASK;
652
653 if (product != PRR_PRODUCT_E3)
654 rcar_pwrc_set_self_refresh();
655 else
656 rcar_pwrc_set_self_refresh_e3();
657
658 #if PMIC_ROHM_BD9571
659 /* Set QLLM Cnt Disable */
660 for (i = 0; (i < PMIC_RETRY_MAX) && (qllm != 0); i++)
661 qllm = rcar_iic_dvfs_send(PMIC, PMIC_QLLM_CNT, 0);
662
663 /* Set trigger of power down to PMIV */
664 for (i = 0; (i < PMIC_RETRY_MAX) && (rc != 0) && (qllm == 0); i++) {
665 rc = rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode);
666 if (rc == 0) {
667 mode |= BIT_BKUP_CTRL_OUT;
668 rc = rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode);
669 }
670 }
671 #endif
672 wfi();
673
674 while (1)
675 ;
676 }
677
rcar_pwrc_set_suspend_to_ram(void)678 void rcar_pwrc_set_suspend_to_ram(void)
679 {
680 uintptr_t jump = (uintptr_t) &rcar_pwrc_go_suspend_to_ram;
681 uintptr_t stack = (uintptr_t) (DEVICE_SRAM_STACK_BASE +
682 DEVICE_SRAM_STACK_SIZE);
683 uint32_t sctlr;
684
685 rcar_pwrc_save_timer_state();
686
687 /* disable MMU */
688 sctlr = (uint32_t) read_sctlr_el3();
689 sctlr &= (uint32_t) ~SCTLR_EL3_M_BIT;
690 write_sctlr_el3((uint64_t) sctlr);
691
692 rcar_pwrc_switch_stack(jump, stack, NULL);
693 }
694
rcar_pwrc_init_suspend_to_ram(void)695 void rcar_pwrc_init_suspend_to_ram(void)
696 {
697 #if PMIC_ROHM_BD9571
698 uint8_t mode;
699
700 if (rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode))
701 panic();
702
703 mode &= (uint8_t) (~BIT_BKUP_CTRL_OUT);
704 if (rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode))
705 panic();
706 #endif
707 }
708
rcar_pwrc_suspend_to_ram(void)709 void rcar_pwrc_suspend_to_ram(void)
710 {
711 #if RCAR_SYSTEM_RESET_KEEPON_DDR
712 int32_t error;
713
714 error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, 0);
715 if (error) {
716 ERROR("Failed send KEEP10 init ret=%d \n", error);
717 return;
718 }
719 #endif
720 rcar_pwrc_set_suspend_to_ram();
721 }
722 #endif
723
rcar_pwrc_code_copy_to_system_ram(void)724 void rcar_pwrc_code_copy_to_system_ram(void)
725 {
726 int ret __attribute__ ((unused)); /* in assert */
727 uint32_t attr;
728 struct device_sram_t {
729 uintptr_t base;
730 size_t len;
731 } sram = {
732 .base = (uintptr_t) DEVICE_SRAM_BASE,
733 .len = DEVICE_SRAM_SIZE,
734 };
735 struct ddr_code_t {
736 void *base;
737 size_t len;
738 } code = {
739 .base = (void *) SRAM_COPY_START,
740 .len = SYSTEM_RAM_END - SYSTEM_RAM_START,
741 };
742
743 attr = MT_MEMORY | MT_RW | MT_SECURE | MT_EXECUTE_NEVER;
744 ret = xlat_change_mem_attributes(sram.base, sram.len, attr);
745 assert(ret == 0);
746
747 memcpy((void *)sram.base, code.base, code.len);
748 flush_dcache_range((uint64_t) sram.base, code.len);
749
750 /* Invalidate instruction cache */
751 plat_invalidate_icache();
752 dsb();
753 isb();
754
755 attr = MT_MEMORY | MT_RO | MT_SECURE | MT_EXECUTE;
756 ret = xlat_change_mem_attributes(sram.base, sram.len, attr);
757 assert(ret == 0);
758 }
759
rcar_pwrc_get_cluster(void)760 uint32_t rcar_pwrc_get_cluster(void)
761 {
762 uint32_t reg;
763
764 reg = mmio_read_32(RCAR_PRR);
765
766 if (reg & (1U << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
767 return RCAR_CLUSTER_CA57;
768
769 if (reg & (1U << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
770 return RCAR_CLUSTER_CA53;
771
772 return RCAR_CLUSTER_A53A57;
773 }
774
rcar_pwrc_get_mpidr_cluster(uint64_t mpidr)775 uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr)
776 {
777 uint32_t c = rcar_pwrc_get_cluster();
778
779 if (IS_A53A57(c)) {
780 if (mpidr & MPIDR_CLUSTER_MASK)
781 return RCAR_CLUSTER_CA53;
782
783 return RCAR_CLUSTER_CA57;
784 }
785
786 return c;
787 }
788
789 #if RCAR_LSI == RCAR_D3
rcar_pwrc_get_cpu_num(uint32_t c)790 uint32_t rcar_pwrc_get_cpu_num(uint32_t c)
791 {
792 return 1;
793 }
794 #else
rcar_pwrc_get_cpu_num(uint32_t c)795 uint32_t rcar_pwrc_get_cpu_num(uint32_t c)
796 {
797 uint32_t reg = mmio_read_32(RCAR_PRR);
798 uint32_t count = 0, i;
799
800 if (IS_A53A57(c) || IS_CA53(c)) {
801 if (reg & (1 << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
802 goto count_ca57;
803
804 for (i = 0; i < RCAR_CA53CPU_NUM_MAX; i++) {
805 if (reg & (1 << (STATE_CA53_CPU + i)))
806 continue;
807 count++;
808 }
809 }
810
811 count_ca57:
812 if (IS_A53A57(c) || IS_CA57(c)) {
813 if (reg & (1U << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
814 goto done;
815
816 for (i = 0; i < RCAR_CA57CPU_NUM_MAX; i++) {
817 if (reg & (1 << (STATE_CA57_CPU + i)))
818 continue;
819 count++;
820 }
821 }
822
823 done:
824 return count;
825 }
826 #endif
827
rcar_pwrc_cpu_on_check(uint64_t mpidr)828 int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr)
829 {
830 uint64_t i;
831 uint64_t j;
832 uint64_t cpu_count;
833 uintptr_t reg_PSTR;
834 uint32_t status;
835 uint64_t my_cpu;
836 int32_t rtn;
837 uint32_t my_cluster_type;
838
839 const uint32_t cluster_type[PLATFORM_CLUSTER_COUNT] = {
840 RCAR_CLUSTER_CA53,
841 RCAR_CLUSTER_CA57
842 };
843 const uintptr_t registerPSTR[PLATFORM_CLUSTER_COUNT] = {
844 RCAR_CA53PSTR,
845 RCAR_CA57PSTR
846 };
847
848 my_cluster_type = rcar_pwrc_get_cluster();
849
850 rtn = 0;
851 my_cpu = mpidr & ((uint64_t)(MPIDR_CPU_MASK));
852 for (i = 0U; i < ((uint64_t)(PLATFORM_CLUSTER_COUNT)); i++) {
853 cpu_count = rcar_pwrc_get_cpu_num(cluster_type[i]);
854 reg_PSTR = registerPSTR[i];
855 for (j = 0U; j < cpu_count; j++) {
856 if ((my_cluster_type != cluster_type[i]) || (my_cpu != j)) {
857 status = mmio_read_32(reg_PSTR) >> (j * 4U);
858 if ((status & 0x00000003U) == 0U) {
859 rtn--;
860 }
861 }
862 }
863 }
864 return (rtn);
865
866 }
867