1 /*
2 * Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9 #include <stdbool.h>
10
11 #include <libfdt.h>
12
13 #include <platform_def.h>
14
15 #include <common/bl_common.h>
16 #include <common/debug.h>
17 #include <drivers/st/stm32_gpio.h>
18 #include <drivers/st/stm32mp_clkfunc.h>
19 #include <lib/mmio.h>
20 #include <lib/utils_def.h>
21
22 #define DT_GPIO_BANK_SHIFT 12
23 #define DT_GPIO_BANK_MASK GENMASK(16, 12)
24 #define DT_GPIO_PIN_SHIFT 8
25 #define DT_GPIO_PIN_MASK GENMASK(11, 8)
26 #define DT_GPIO_MODE_MASK GENMASK(7, 0)
27
28 /*******************************************************************************
29 * This function gets GPIO bank node in DT.
30 * Returns node offset if status is okay in DT, else return 0
31 ******************************************************************************/
ckeck_gpio_bank(void * fdt,uint32_t bank,int pinctrl_node)32 static int ckeck_gpio_bank(void *fdt, uint32_t bank, int pinctrl_node)
33 {
34 int pinctrl_subnode;
35 uint32_t bank_offset = stm32_get_gpio_bank_offset(bank);
36
37 fdt_for_each_subnode(pinctrl_subnode, fdt, pinctrl_node) {
38 const fdt32_t *cuint;
39
40 if (fdt_getprop(fdt, pinctrl_subnode,
41 "gpio-controller", NULL) == NULL) {
42 continue;
43 }
44
45 cuint = fdt_getprop(fdt, pinctrl_subnode, "reg", NULL);
46 if (cuint == NULL) {
47 continue;
48 }
49
50 if ((fdt32_to_cpu(*cuint) == bank_offset) &&
51 (fdt_get_status(pinctrl_subnode) != DT_DISABLED)) {
52 return pinctrl_subnode;
53 }
54 }
55
56 return 0;
57 }
58
59 /*******************************************************************************
60 * This function gets the pin settings from DT information.
61 * When analyze and parsing is done, set the GPIO registers.
62 * Returns 0 on success and a negative FDT error code on failure.
63 ******************************************************************************/
dt_set_gpio_config(void * fdt,int node,uint8_t status)64 static int dt_set_gpio_config(void *fdt, int node, uint8_t status)
65 {
66 const fdt32_t *cuint, *slewrate;
67 int len;
68 int pinctrl_node;
69 uint32_t i;
70 uint32_t speed = GPIO_SPEED_LOW;
71 uint32_t pull = GPIO_NO_PULL;
72
73 cuint = fdt_getprop(fdt, node, "pinmux", &len);
74 if (cuint == NULL) {
75 return -FDT_ERR_NOTFOUND;
76 }
77
78 pinctrl_node = fdt_parent_offset(fdt, fdt_parent_offset(fdt, node));
79 if (pinctrl_node < 0) {
80 return -FDT_ERR_NOTFOUND;
81 }
82
83 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL);
84 if (slewrate != NULL) {
85 speed = fdt32_to_cpu(*slewrate);
86 }
87
88 if (fdt_getprop(fdt, node, "bias-pull-up", NULL) != NULL) {
89 pull = GPIO_PULL_UP;
90 } else if (fdt_getprop(fdt, node, "bias-pull-down", NULL) != NULL) {
91 pull = GPIO_PULL_DOWN;
92 } else {
93 VERBOSE("No bias configured in node %d\n", node);
94 }
95
96 for (i = 0U; i < ((uint32_t)len / sizeof(uint32_t)); i++) {
97 uint32_t pincfg;
98 uint32_t bank;
99 uint32_t pin;
100 uint32_t mode;
101 uint32_t alternate = GPIO_ALTERNATE_(0);
102 int bank_node;
103 int clk;
104
105 pincfg = fdt32_to_cpu(*cuint);
106 cuint++;
107
108 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT;
109
110 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT;
111
112 mode = pincfg & DT_GPIO_MODE_MASK;
113
114 switch (mode) {
115 case 0:
116 mode = GPIO_MODE_INPUT;
117 break;
118 case 1 ... 16:
119 alternate = mode - 1U;
120 mode = GPIO_MODE_ALTERNATE;
121 break;
122 case 17:
123 mode = GPIO_MODE_ANALOG;
124 break;
125 default:
126 mode = GPIO_MODE_OUTPUT;
127 break;
128 }
129
130 if (fdt_getprop(fdt, node, "drive-open-drain", NULL) != NULL) {
131 mode |= GPIO_OPEN_DRAIN;
132 }
133
134 bank_node = ckeck_gpio_bank(fdt, bank, pinctrl_node);
135 if (bank_node == 0) {
136 ERROR("PINCTRL inconsistent in DT\n");
137 panic();
138 }
139
140 clk = fdt_get_clock_id(bank_node);
141 if (clk < 0) {
142 return -FDT_ERR_NOTFOUND;
143 }
144
145 /* Platform knows the clock: assert it is okay */
146 assert((unsigned long)clk == stm32_get_gpio_bank_clock(bank));
147
148 set_gpio(bank, pin, mode, speed, pull, alternate, status);
149 }
150
151 return 0;
152 }
153
154 /*******************************************************************************
155 * This function gets the pin settings from DT information.
156 * When analyze and parsing is done, set the GPIO registers.
157 * Returns 0 on success and a negative FDT/ERRNO error code on failure.
158 ******************************************************************************/
dt_set_pinctrl_config(int node)159 int dt_set_pinctrl_config(int node)
160 {
161 const fdt32_t *cuint;
162 int lenp = 0;
163 uint32_t i;
164 uint8_t status = fdt_get_status(node);
165 void *fdt;
166
167 if (fdt_get_address(&fdt) == 0) {
168 return -FDT_ERR_NOTFOUND;
169 }
170
171 if (status == DT_DISABLED) {
172 return -FDT_ERR_NOTFOUND;
173 }
174
175 cuint = fdt_getprop(fdt, node, "pinctrl-0", &lenp);
176 if (cuint == NULL) {
177 return -FDT_ERR_NOTFOUND;
178 }
179
180 for (i = 0; i < ((uint32_t)lenp / 4U); i++) {
181 int p_node, p_subnode;
182
183 p_node = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint));
184 if (p_node < 0) {
185 return -FDT_ERR_NOTFOUND;
186 }
187
188 fdt_for_each_subnode(p_subnode, fdt, p_node) {
189 int ret = dt_set_gpio_config(fdt, p_subnode, status);
190
191 if (ret < 0) {
192 return ret;
193 }
194 }
195
196 cuint++;
197 }
198
199 return 0;
200 }
201
set_gpio(uint32_t bank,uint32_t pin,uint32_t mode,uint32_t speed,uint32_t pull,uint32_t alternate,uint8_t status)202 void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
203 uint32_t pull, uint32_t alternate, uint8_t status)
204 {
205 uintptr_t base = stm32_get_gpio_bank_base(bank);
206 unsigned long clock = stm32_get_gpio_bank_clock(bank);
207
208 assert(pin <= GPIO_PIN_MAX);
209
210 stm32mp_clk_enable(clock);
211
212 mmio_clrbits_32(base + GPIO_MODE_OFFSET,
213 ((uint32_t)GPIO_MODE_MASK << (pin << 1)));
214 mmio_setbits_32(base + GPIO_MODE_OFFSET,
215 (mode & ~GPIO_OPEN_DRAIN) << (pin << 1));
216
217 if ((mode & GPIO_OPEN_DRAIN) != 0U) {
218 mmio_setbits_32(base + GPIO_TYPE_OFFSET, BIT(pin));
219 } else {
220 mmio_clrbits_32(base + GPIO_TYPE_OFFSET, BIT(pin));
221 }
222
223 mmio_clrbits_32(base + GPIO_SPEED_OFFSET,
224 ((uint32_t)GPIO_SPEED_MASK << (pin << 1)));
225 mmio_setbits_32(base + GPIO_SPEED_OFFSET, speed << (pin << 1));
226
227 mmio_clrbits_32(base + GPIO_PUPD_OFFSET,
228 ((uint32_t)GPIO_PULL_MASK << (pin << 1)));
229 mmio_setbits_32(base + GPIO_PUPD_OFFSET, pull << (pin << 1));
230
231 if (pin < GPIO_ALT_LOWER_LIMIT) {
232 mmio_clrbits_32(base + GPIO_AFRL_OFFSET,
233 ((uint32_t)GPIO_ALTERNATE_MASK << (pin << 2)));
234 mmio_setbits_32(base + GPIO_AFRL_OFFSET,
235 alternate << (pin << 2));
236 } else {
237 mmio_clrbits_32(base + GPIO_AFRH_OFFSET,
238 ((uint32_t)GPIO_ALTERNATE_MASK <<
239 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)));
240 mmio_setbits_32(base + GPIO_AFRH_OFFSET,
241 alternate << ((pin - GPIO_ALT_LOWER_LIMIT) <<
242 2));
243 }
244
245 VERBOSE("GPIO %u mode set to 0x%x\n", bank,
246 mmio_read_32(base + GPIO_MODE_OFFSET));
247 VERBOSE("GPIO %u speed set to 0x%x\n", bank,
248 mmio_read_32(base + GPIO_SPEED_OFFSET));
249 VERBOSE("GPIO %u mode pull to 0x%x\n", bank,
250 mmio_read_32(base + GPIO_PUPD_OFFSET));
251 VERBOSE("GPIO %u mode alternate low to 0x%x\n", bank,
252 mmio_read_32(base + GPIO_AFRL_OFFSET));
253 VERBOSE("GPIO %u mode alternate high to 0x%x\n", bank,
254 mmio_read_32(base + GPIO_AFRH_OFFSET));
255
256 stm32mp_clk_disable(clock);
257 }
258
set_gpio_secure_cfg(uint32_t bank,uint32_t pin,bool secure)259 void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure)
260 {
261 uintptr_t base = stm32_get_gpio_bank_base(bank);
262 unsigned long clock = stm32_get_gpio_bank_clock(bank);
263
264 assert(pin <= GPIO_PIN_MAX);
265
266 stm32mp_clk_enable(clock);
267
268 if (secure) {
269 mmio_setbits_32(base + GPIO_SECR_OFFSET, BIT(pin));
270 } else {
271 mmio_clrbits_32(base + GPIO_SECR_OFFSET, BIT(pin));
272 }
273
274 stm32mp_clk_disable(clock);
275 }
276