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1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017-2019 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/pinctrl/stm32-pinfunc.h>
7
8/ {
9	soc {
10		pinctrl: pin-controller@50002000 {
11			#address-cells = <1>;
12			#size-cells = <1>;
13			compatible = "st,stm32mp157-pinctrl";
14			ranges = <0 0x50002000 0xa400>;
15			pins-are-numbered;
16
17			gpioa: gpio@50002000 {
18				gpio-controller;
19				#gpio-cells = <2>;
20				interrupt-controller;
21				#interrupt-cells = <2>;
22				reg = <0x0 0x400>;
23				clocks = <&rcc GPIOA>;
24				st,bank-name = "GPIOA";
25				status = "disabled";
26			};
27
28			gpiob: gpio@50003000 {
29				gpio-controller;
30				#gpio-cells = <2>;
31				interrupt-controller;
32				#interrupt-cells = <2>;
33				reg = <0x1000 0x400>;
34				clocks = <&rcc GPIOB>;
35				st,bank-name = "GPIOB";
36				status = "disabled";
37			};
38
39			gpioc: gpio@50004000 {
40				gpio-controller;
41				#gpio-cells = <2>;
42				interrupt-controller;
43				#interrupt-cells = <2>;
44				reg = <0x2000 0x400>;
45				clocks = <&rcc GPIOC>;
46				st,bank-name = "GPIOC";
47				status = "disabled";
48			};
49
50			gpiod: gpio@50005000 {
51				gpio-controller;
52				#gpio-cells = <2>;
53				interrupt-controller;
54				#interrupt-cells = <2>;
55				reg = <0x3000 0x400>;
56				clocks = <&rcc GPIOD>;
57				st,bank-name = "GPIOD";
58				status = "disabled";
59			};
60
61			gpioe: gpio@50006000 {
62				gpio-controller;
63				#gpio-cells = <2>;
64				interrupt-controller;
65				#interrupt-cells = <2>;
66				reg = <0x4000 0x400>;
67				clocks = <&rcc GPIOE>;
68				st,bank-name = "GPIOE";
69				status = "disabled";
70			};
71
72			gpiof: gpio@50007000 {
73				gpio-controller;
74				#gpio-cells = <2>;
75				interrupt-controller;
76				#interrupt-cells = <2>;
77				reg = <0x5000 0x400>;
78				clocks = <&rcc GPIOF>;
79				st,bank-name = "GPIOF";
80				status = "disabled";
81			};
82
83			gpiog: gpio@50008000 {
84				gpio-controller;
85				#gpio-cells = <2>;
86				interrupt-controller;
87				#interrupt-cells = <2>;
88				reg = <0x6000 0x400>;
89				clocks = <&rcc GPIOG>;
90				st,bank-name = "GPIOG";
91				status = "disabled";
92			};
93
94			gpioh: gpio@50009000 {
95				gpio-controller;
96				#gpio-cells = <2>;
97				interrupt-controller;
98				#interrupt-cells = <2>;
99				reg = <0x7000 0x400>;
100				clocks = <&rcc GPIOH>;
101				st,bank-name = "GPIOH";
102				status = "disabled";
103			};
104
105			gpioi: gpio@5000a000 {
106				gpio-controller;
107				#gpio-cells = <2>;
108				interrupt-controller;
109				#interrupt-cells = <2>;
110				reg = <0x8000 0x400>;
111				clocks = <&rcc GPIOI>;
112				st,bank-name = "GPIOI";
113				status = "disabled";
114			};
115
116			gpioj: gpio@5000b000 {
117				gpio-controller;
118				#gpio-cells = <2>;
119				interrupt-controller;
120				#interrupt-cells = <2>;
121				reg = <0x9000 0x400>;
122				clocks = <&rcc GPIOJ>;
123				st,bank-name = "GPIOJ";
124				status = "disabled";
125			};
126
127			gpiok: gpio@5000c000 {
128				gpio-controller;
129				#gpio-cells = <2>;
130				interrupt-controller;
131				#interrupt-cells = <2>;
132				reg = <0xa000 0x400>;
133				clocks = <&rcc GPIOK>;
134				st,bank-name = "GPIOK";
135				status = "disabled";
136			};
137
138			fmc_pins_a: fmc-0 {
139				pins1 {
140					pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
141						 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
142						 <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
143						 <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
144						 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
145						 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
146						 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
147						 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
148						 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
149						 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
150						 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
151						 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
152						 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
153					bias-disable;
154					drive-push-pull;
155					slew-rate = <1>;
156				};
157				pins2 {
158					pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
159					bias-pull-up;
160				};
161			};
162
163			qspi_bk1_pins_a: qspi-bk1-0 {
164				pins1 {
165					pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
166						 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
167						 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
168						 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
169					bias-disable;
170					drive-push-pull;
171					slew-rate = <1>;
172				};
173				pins2 {
174					pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
175					bias-pull-up;
176					drive-push-pull;
177					slew-rate = <1>;
178				};
179			};
180
181			qspi_bk2_pins_a: qspi-bk2-0 {
182				pins1 {
183					pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
184						 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
185						 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
186						 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
187					bias-disable;
188					drive-push-pull;
189					slew-rate = <1>;
190				};
191				pins2 {
192					pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
193					bias-pull-up;
194					drive-push-pull;
195					slew-rate = <1>;
196				};
197			};
198
199			qspi_clk_pins_a: qspi-clk-0 {
200				pins {
201					pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
202					bias-disable;
203					drive-push-pull;
204					slew-rate = <3>;
205				};
206			};
207
208			sdmmc1_b4_pins_a: sdmmc1-b4-0 {
209				pins1 {
210					pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
211						 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
212						 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
213						 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
214						 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
215					slew-rate = <1>;
216					drive-push-pull;
217					bias-disable;
218				};
219				pins2 {
220					pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
221					slew-rate = <2>;
222					drive-push-pull;
223					bias-disable;
224				};
225			};
226
227			sdmmc1_dir_pins_a: sdmmc1-dir-0 {
228				pins1 {
229					pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
230						 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
231						 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
232					slew-rate = <1>;
233					drive-push-pull;
234					bias-pull-up;
235				};
236				pins2{
237					pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
238					bias-pull-up;
239				};
240			};
241
242			sdmmc2_b4_pins_a: sdmmc2-b4-0 {
243				pins1 {
244					pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
245						 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
246						 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
247						 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
248						 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
249					slew-rate = <1>;
250					drive-push-pull;
251					bias-pull-up;
252				};
253				pins2 {
254					pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
255					slew-rate = <2>;
256					drive-push-pull;
257					bias-pull-up;
258				};
259			};
260
261			sdmmc2_d47_pins_a: sdmmc2-d47-0 {
262				pins {
263					pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
264						 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
265						 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
266						 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
267					slew-rate = <1>;
268					drive-push-pull;
269					bias-pull-up;
270				};
271			};
272
273			uart4_pins_a: uart4-0 {
274				pins1 {
275					pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
276					bias-disable;
277					drive-push-pull;
278					slew-rate = <0>;
279				};
280				pins2 {
281					pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
282					bias-disable;
283				};
284			};
285
286			uart4_pins_b: uart4-1 {
287				pins1 {
288					pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
289					bias-disable;
290					drive-push-pull;
291					slew-rate = <0>;
292				};
293				pins2 {
294					pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
295					bias-disable;
296				};
297			};
298
299			uart7_pins_a: uart7-0 {
300				pins1 {
301					pinmux = <STM32_PINMUX('E', 8, AF7)>; /* USART7_TX */
302					bias-disable;
303					drive-push-pull;
304					slew-rate = <0>;
305				};
306				pins2 {
307					pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
308					bias-disable;
309				};
310			};
311
312			usart3_pins_a: usart3-0 {
313				pins1 {
314					pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
315						 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
316					bias-disable;
317					drive-push-pull;
318					slew-rate = <0>;
319				};
320				pins2 {
321					pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
322						 <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
323					bias-disable;
324				};
325			};
326
327			usart3_pins_b: usart3-1 {
328				pins1 {
329					pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
330						 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
331					bias-disable;
332					drive-push-pull;
333					slew-rate = <0>;
334				};
335				pins2 {
336					pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
337						 <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
338					bias-disable;
339				};
340			};
341		};
342
343		pinctrl_z: pin-controller-z@54004000 {
344			#address-cells = <1>;
345			#size-cells = <1>;
346			compatible = "st,stm32mp157-z-pinctrl";
347			ranges = <0 0x54004000 0x400>;
348			pins-are-numbered;
349
350			gpioz: gpio@54004000 {
351				gpio-controller;
352				#gpio-cells = <2>;
353				interrupt-controller;
354				#interrupt-cells = <2>;
355				reg = <0 0x400>;
356				clocks = <&rcc GPIOZ>;
357				st,bank-name = "GPIOZ";
358				st,bank-ioport = <11>;
359				status = "disabled";
360			};
361
362			i2c4_pins_a: i2c4-0 {
363				pins {
364					pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
365						 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
366					bias-disable;
367					drive-open-drain;
368					slew-rate = <0>;
369				};
370			};
371		};
372	};
373};
374