1 /* 2 * Copyright (c) 2019, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef DRIVERS_RAW_NAND_H 8 #define DRIVERS_RAW_NAND_H 9 10 #include <stdint.h> 11 12 #include <drivers/nand.h> 13 14 /* NAND ONFI default value mode 0 in picosecond */ 15 #define NAND_TADL_MIN 400000UL 16 #define NAND_TALH_MIN 20000UL 17 #define NAND_TALS_MIN 50000UL 18 #define NAND_TAR_MIN 25000UL 19 #define NAND_TCCS_MIN 500000UL 20 #define NAND_TCEA_MIN 100000UL 21 #define NAND_TCEH_MIN 20000UL 22 #define NAND_TCH_MIN 20000UL 23 #define NAND_TCHZ_MAX 100000UL 24 #define NAND_TCLH_MIN 20000UL 25 #define NAND_TCLR_MIN 20000UL 26 #define NAND_TCLS_MIN 50000UL 27 #define NAND_TCOH_MIN 0UL 28 #define NAND_TCS_MIN 70000UL 29 #define NAND_TDH_MIN 20000UL 30 #define NAND_TDS_MIN 40000UL 31 #define NAND_TFEAT_MAX 1000000UL 32 #define NAND_TIR_MIN 10000UL 33 #define NAND_TITC_MIN 1000000UL 34 #define NAND_TR_MAX 200000000UL 35 #define NAND_TRC_MIN 100000UL 36 #define NAND_TREA_MAX 40000UL 37 #define NAND_TREH_MIN 30000UL 38 #define NAND_TRHOH_MIN 0UL 39 #define NAND_TRHW_MIN 200000UL 40 #define NAND_TRHZ_MAX 200000UL 41 #define NAND_TRLOH_MIN 0UL 42 #define NAND_TRP_MIN 50000UL 43 #define NAND_TRR_MIN 40000UL 44 #define NAND_TRST_MAX 250000000000ULL 45 #define NAND_TWB_MAX 200000UL 46 #define NAND_TWC_MIN 100000UL 47 #define NAND_TWH_MIN 30000UL 48 #define NAND_TWHR_MIN 120000UL 49 #define NAND_TWP_MIN 50000UL 50 #define NAND_TWW_MIN 100000UL 51 52 /* NAND request types */ 53 #define NAND_REQ_CMD 0x0000U 54 #define NAND_REQ_ADDR 0x1000U 55 #define NAND_REQ_DATAIN 0x2000U 56 #define NAND_REQ_DATAOUT 0x3000U 57 #define NAND_REQ_WAIT 0x4000U 58 #define NAND_REQ_MASK GENMASK(14, 12) 59 #define NAND_REQ_BUS_WIDTH_8 BIT(15) 60 61 #define PARAM_PAGE_SIZE 256 62 63 /* NAND ONFI commands */ 64 #define NAND_CMD_READ_1ST 0x00U 65 #define NAND_CMD_CHANGE_1ST 0x05U 66 #define NAND_CMD_READID_SIG_ADDR 0x20U 67 #define NAND_CMD_READ_2ND 0x30U 68 #define NAND_CMD_STATUS 0x70U 69 #define NAND_CMD_READID 0x90U 70 #define NAND_CMD_CHANGE_2ND 0xE0U 71 #define NAND_CMD_READ_PARAM_PAGE 0xECU 72 #define NAND_CMD_RESET 0xFFU 73 74 #define ONFI_REV_21 BIT(3) 75 #define ONFI_FEAT_BUS_WIDTH_16 BIT(0) 76 #define ONFI_FEAT_EXTENDED_PARAM BIT(7) 77 78 /* NAND ECC type */ 79 #define NAND_ECC_NONE U(0) 80 #define NAND_ECC_HW U(1) 81 #define NAND_ECC_ONDIE U(2) 82 83 /* NAND bus width */ 84 #define NAND_BUS_WIDTH_8 U(0) 85 #define NAND_BUS_WIDTH_16 U(1) 86 87 struct nand_req { 88 struct nand_device *nand; 89 uint16_t type; 90 uint8_t *addr; 91 unsigned int length; 92 unsigned int delay_ms; 93 unsigned int inst_delay; 94 }; 95 96 struct nand_param_page { 97 /* Rev information and feature block */ 98 uint32_t page_sig; 99 uint16_t rev; 100 uint16_t features; 101 uint16_t opt_cmd; 102 uint8_t jtg; 103 uint8_t train_cmd; 104 uint16_t ext_param_length; 105 uint8_t nb_param_pages; 106 uint8_t reserved1[17]; 107 /* Manufacturer information */ 108 uint8_t manufacturer[12]; 109 uint8_t model[20]; 110 uint8_t manufacturer_id; 111 uint16_t data_code; 112 uint8_t reserved2[13]; 113 /* Memory organization */ 114 uint32_t bytes_per_page; 115 uint16_t spare_per_page; 116 uint32_t bytes_per_partial; 117 uint16_t spare_per_partial; 118 uint32_t num_pages_per_blk; 119 uint32_t num_blk_in_lun; 120 uint8_t num_lun; 121 uint8_t num_addr_cycles; 122 uint8_t bit_per_cell; 123 uint16_t max_bb_per_lun; 124 uint16_t blk_endur; 125 uint8_t valid_blk_begin; 126 uint16_t blk_enbur_valid; 127 uint8_t nb_prog_page; 128 uint8_t partial_prog_attr; 129 uint8_t nb_ecc_bits; 130 uint8_t plane_addr; 131 uint8_t mplanes_ops; 132 uint8_t ez_nand; 133 uint8_t reserved3[12]; 134 /* Electrical parameters */ 135 uint8_t io_pin_cap_max; 136 uint16_t sdr_timing_mode; 137 uint16_t sdr_prog_cache_timing; 138 uint16_t tprog; 139 uint16_t tbers; 140 uint16_t tr; 141 uint16_t tccs; 142 uint8_t nvddr_timing_mode; 143 uint8_t nvddr2_timing_mode; 144 uint8_t nvddr_features; 145 uint16_t clk_input_cap_typ; 146 uint16_t io_pin_cap_typ; 147 uint16_t input_pin_cap_typ; 148 uint8_t input_pin_cap_max; 149 uint8_t drv_strength_support; 150 uint16_t tr_max; 151 uint16_t tadl; 152 uint16_t tr_typ; 153 uint8_t reserved4[6]; 154 /* Vendor block */ 155 uint16_t vendor_revision; 156 uint8_t vendor[88]; 157 uint16_t crc16; 158 } __packed; 159 160 struct nand_ctrl_ops { 161 int (*exec)(struct nand_req *req); 162 void (*setup)(struct nand_device *nand); 163 }; 164 165 struct rawnand_device { 166 struct nand_device *nand_dev; 167 const struct nand_ctrl_ops *ops; 168 }; 169 170 int nand_raw_init(unsigned long long *size, unsigned int *erase_size); 171 int nand_wait_ready(unsigned long delay); 172 int nand_read_page_cmd(unsigned int page, unsigned int offset, 173 uintptr_t buffer, unsigned int len); 174 int nand_change_read_column_cmd(unsigned int offset, uintptr_t buffer, 175 unsigned int len); 176 void nand_raw_ctrl_init(const struct nand_ctrl_ops *ops); 177 178 /* 179 * Platform can implement this to override default raw NAND instance 180 * configuration. 181 * 182 * @device: target raw NAND instance. 183 * Return 0 on success, negative value otherwise. 184 */ 185 int plat_get_raw_nand_data(struct rawnand_device *device); 186 187 #endif /* DRIVERS_RAW_NAND_H */ 188