1/* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <cortex_a72.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12 13 /* --------------------------------------------- 14 * Disable L1 data cache and unified L2 cache 15 * --------------------------------------------- 16 */ 17func cortex_a72_disable_dcache 18 mrs x1, sctlr_el3 19 bic x1, x1, #SCTLR_C_BIT 20 msr sctlr_el3, x1 21 isb 22 ret 23endfunc cortex_a72_disable_dcache 24 25 /* --------------------------------------------- 26 * Disable all types of L2 prefetches. 27 * --------------------------------------------- 28 */ 29func cortex_a72_disable_l2_prefetch 30 mrs x0, CORTEX_A72_ECTLR_EL1 31 orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT 32 mov x1, #CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK 33 orr x1, x1, #CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK 34 bic x0, x0, x1 35 msr CORTEX_A72_ECTLR_EL1, x0 36 isb 37 ret 38endfunc cortex_a72_disable_l2_prefetch 39 40 /* --------------------------------------------- 41 * Disable the load-store hardware prefetcher. 42 * --------------------------------------------- 43 */ 44func cortex_a72_disable_hw_prefetcher 45 mrs x0, CORTEX_A72_CPUACTLR_EL1 46 orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH 47 msr CORTEX_A72_CPUACTLR_EL1, x0 48 isb 49 dsb ish 50 ret 51endfunc cortex_a72_disable_hw_prefetcher 52 53 /* --------------------------------------------- 54 * Disable intra-cluster coherency 55 * --------------------------------------------- 56 */ 57func cortex_a72_disable_smp 58 mrs x0, CORTEX_A72_ECTLR_EL1 59 bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT 60 msr CORTEX_A72_ECTLR_EL1, x0 61 ret 62endfunc cortex_a72_disable_smp 63 64 /* --------------------------------------------- 65 * Disable debug interfaces 66 * --------------------------------------------- 67 */ 68func cortex_a72_disable_ext_debug 69 mov x0, #1 70 msr osdlr_el1, x0 71 isb 72 dsb sy 73 ret 74endfunc cortex_a72_disable_ext_debug 75 76 /* -------------------------------------------------- 77 * Errata Workaround for Cortex A72 Errata #859971. 78 * This applies only to revision <= r0p3 of Cortex A72. 79 * Inputs: 80 * x0: variant[4:7] and revision[0:3] of current cpu. 81 * Shall clobber: 82 * -------------------------------------------------- 83 */ 84func errata_a72_859971_wa 85 mov x17,x30 86 bl check_errata_859971 87 cbz x0, 1f 88 mrs x1, CORTEX_A72_CPUACTLR_EL1 89 orr x1, x1, #CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH 90 msr CORTEX_A72_CPUACTLR_EL1, x1 911: 92 ret x17 93endfunc errata_a72_859971_wa 94 95func check_errata_859971 96 mov x1, #0x03 97 b cpu_rev_var_ls 98endfunc check_errata_859971 99 100func check_errata_cve_2017_5715 101 cpu_check_csv2 x0, 1f 102#if WORKAROUND_CVE_2017_5715 103 mov x0, #ERRATA_APPLIES 104#else 105 mov x0, #ERRATA_MISSING 106#endif 107 ret 1081: 109 mov x0, #ERRATA_NOT_APPLIES 110 ret 111endfunc check_errata_cve_2017_5715 112 113func check_errata_cve_2018_3639 114#if WORKAROUND_CVE_2018_3639 115 mov x0, #ERRATA_APPLIES 116#else 117 mov x0, #ERRATA_MISSING 118#endif 119 ret 120endfunc check_errata_cve_2018_3639 121 122 /* ------------------------------------------------- 123 * The CPU Ops reset function for Cortex-A72. 124 * ------------------------------------------------- 125 */ 126func cortex_a72_reset_func 127 mov x19, x30 128 bl cpu_get_rev_var 129 mov x18, x0 130 131#if ERRATA_A72_859971 132 mov x0, x18 133 bl errata_a72_859971_wa 134#endif 135 136#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 137 cpu_check_csv2 x0, 1f 138 adr x0, wa_cve_2017_5715_mmu_vbar 139 msr vbar_el3, x0 140 /* isb will be performed before returning from this function */ 1411: 142#endif 143 144#if WORKAROUND_CVE_2018_3639 145 mrs x0, CORTEX_A72_CPUACTLR_EL1 146 orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE 147 msr CORTEX_A72_CPUACTLR_EL1, x0 148 isb 149 dsb sy 150#endif 151 152 /* --------------------------------------------- 153 * Enable the SMP bit. 154 * --------------------------------------------- 155 */ 156 mrs x0, CORTEX_A72_ECTLR_EL1 157 orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT 158 msr CORTEX_A72_ECTLR_EL1, x0 159 isb 160 ret x19 161endfunc cortex_a72_reset_func 162 163 /* ---------------------------------------------------- 164 * The CPU Ops core power down function for Cortex-A72. 165 * ---------------------------------------------------- 166 */ 167func cortex_a72_core_pwr_dwn 168 mov x18, x30 169 170 /* --------------------------------------------- 171 * Turn off caches. 172 * --------------------------------------------- 173 */ 174 bl cortex_a72_disable_dcache 175 176 /* --------------------------------------------- 177 * Disable the L2 prefetches. 178 * --------------------------------------------- 179 */ 180 bl cortex_a72_disable_l2_prefetch 181 182 /* --------------------------------------------- 183 * Disable the load-store hardware prefetcher. 184 * --------------------------------------------- 185 */ 186 bl cortex_a72_disable_hw_prefetcher 187 188 /* --------------------------------------------- 189 * Flush L1 caches. 190 * --------------------------------------------- 191 */ 192 mov x0, #DCCISW 193 bl dcsw_op_level1 194 195 /* --------------------------------------------- 196 * Come out of intra cluster coherency 197 * --------------------------------------------- 198 */ 199 bl cortex_a72_disable_smp 200 201 /* --------------------------------------------- 202 * Force the debug interfaces to be quiescent 203 * --------------------------------------------- 204 */ 205 mov x30, x18 206 b cortex_a72_disable_ext_debug 207endfunc cortex_a72_core_pwr_dwn 208 209 /* ------------------------------------------------------- 210 * The CPU Ops cluster power down function for Cortex-A72. 211 * ------------------------------------------------------- 212 */ 213func cortex_a72_cluster_pwr_dwn 214 mov x18, x30 215 216 /* --------------------------------------------- 217 * Turn off caches. 218 * --------------------------------------------- 219 */ 220 bl cortex_a72_disable_dcache 221 222 /* --------------------------------------------- 223 * Disable the L2 prefetches. 224 * --------------------------------------------- 225 */ 226 bl cortex_a72_disable_l2_prefetch 227 228 /* --------------------------------------------- 229 * Disable the load-store hardware prefetcher. 230 * --------------------------------------------- 231 */ 232 bl cortex_a72_disable_hw_prefetcher 233 234#if !SKIP_A72_L1_FLUSH_PWR_DWN 235 /* --------------------------------------------- 236 * Flush L1 caches. 237 * --------------------------------------------- 238 */ 239 mov x0, #DCCISW 240 bl dcsw_op_level1 241#endif 242 243 /* --------------------------------------------- 244 * Disable the optional ACP. 245 * --------------------------------------------- 246 */ 247 bl plat_disable_acp 248 249 /* ------------------------------------------------- 250 * Flush the L2 caches. 251 * ------------------------------------------------- 252 */ 253 mov x0, #DCCISW 254 bl dcsw_op_level2 255 256 /* --------------------------------------------- 257 * Come out of intra cluster coherency 258 * --------------------------------------------- 259 */ 260 bl cortex_a72_disable_smp 261 262 /* --------------------------------------------- 263 * Force the debug interfaces to be quiescent 264 * --------------------------------------------- 265 */ 266 mov x30, x18 267 b cortex_a72_disable_ext_debug 268endfunc cortex_a72_cluster_pwr_dwn 269 270#if REPORT_ERRATA 271/* 272 * Errata printing function for Cortex A72. Must follow AAPCS. 273 */ 274func cortex_a72_errata_report 275 stp x8, x30, [sp, #-16]! 276 277 bl cpu_get_rev_var 278 mov x8, x0 279 280 /* 281 * Report all errata. The revision-variant information is passed to 282 * checking functions of each errata. 283 */ 284 report_errata ERRATA_A72_859971, cortex_a72, 859971 285 report_errata WORKAROUND_CVE_2017_5715, cortex_a72, cve_2017_5715 286 report_errata WORKAROUND_CVE_2018_3639, cortex_a72, cve_2018_3639 287 288 ldp x8, x30, [sp], #16 289 ret 290endfunc cortex_a72_errata_report 291#endif 292 293 /* --------------------------------------------- 294 * This function provides cortex_a72 specific 295 * register information for crash reporting. 296 * It needs to return with x6 pointing to 297 * a list of register names in ascii and 298 * x8 - x15 having values of registers to be 299 * reported. 300 * --------------------------------------------- 301 */ 302.section .rodata.cortex_a72_regs, "aS" 303cortex_a72_regs: /* The ascii list of register names to be reported */ 304 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" 305 306func cortex_a72_cpu_reg_dump 307 adr x6, cortex_a72_regs 308 mrs x8, CORTEX_A72_ECTLR_EL1 309 mrs x9, CORTEX_A72_MERRSR_EL1 310 mrs x10, CORTEX_A72_L2MERRSR_EL1 311 ret 312endfunc cortex_a72_cpu_reg_dump 313 314declare_cpu_ops_wa cortex_a72, CORTEX_A72_MIDR, \ 315 cortex_a72_reset_func, \ 316 check_errata_cve_2017_5715, \ 317 CPU_NO_EXTRA2_FUNC, \ 318 cortex_a72_core_pwr_dwn, \ 319 cortex_a72_cluster_pwr_dwn 320