1/* 2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a77.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24 /* --------------------------------------------- 25 * HW will do the cache maintenance while powering down 26 * --------------------------------------------- 27 */ 28func cortex_a77_core_pwr_dwn 29 /* --------------------------------------------- 30 * Enable CPU power down bit in power control register 31 * --------------------------------------------- 32 */ 33 mrs x0, CORTEX_A77_CPUPWRCTLR_EL1 34 orr x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 35 msr CORTEX_A77_CPUPWRCTLR_EL1, x0 36 isb 37 ret 38endfunc cortex_a77_core_pwr_dwn 39 40#if REPORT_ERRATA 41/* 42 * Errata printing function for Cortex-A77. Must follow AAPCS. 43 */ 44func cortex_a77_errata_report 45 ret 46endfunc cortex_a77_errata_report 47#endif 48 49 50 /* --------------------------------------------- 51 * This function provides Cortex-A77 specific 52 * register information for crash reporting. 53 * It needs to return with x6 pointing to 54 * a list of register names in ascii and 55 * x8 - x15 having values of registers to be 56 * reported. 57 * --------------------------------------------- 58 */ 59.section .rodata.cortex_a77_regs, "aS" 60cortex_a77_regs: /* The ascii list of register names to be reported */ 61 .asciz "cpuectlr_el1", "" 62 63func cortex_a77_cpu_reg_dump 64 adr x6, cortex_a77_regs 65 mrs x8, CORTEX_A77_CPUECTLR_EL1 66 ret 67endfunc cortex_a77_cpu_reg_dump 68 69declare_cpu_ops cortex_a77, CORTEX_A77_MIDR, \ 70 CPU_NO_RESET_FUNC, \ 71 cortex_a77_core_pwr_dwn 72