1/* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <assert_macros.S> 9#include <asm_macros.S> 10 11 .globl amu_group0_cnt_read_internal 12 .globl amu_group0_cnt_write_internal 13 .globl amu_group1_cnt_read_internal 14 .globl amu_group1_cnt_write_internal 15 .globl amu_group1_set_evtype_internal 16 17/* 18 * uint64_t amu_group0_cnt_read_internal(int idx); 19 * 20 * Given `idx`, read the corresponding AMU counter 21 * and return it in `r0` and `r1`. 22 */ 23func amu_group0_cnt_read_internal 24#if ENABLE_ASSERTIONS 25 /* `idx` should be between [0, 3] */ 26 mov r1, r0 27 lsr r1, r1, #2 28 cmp r1, #0 29 ASM_ASSERT(eq) 30#endif 31 32 /* 33 * Given `idx` calculate address of ldcopr16/bx lr instruction pair 34 * in the table below. 35 */ 36 adr r1, 1f 37 lsl r0, r0, #3 /* each ldcopr16/bx lr sequence is 8 bytes */ 38 add r1, r1, r0 39 bx r1 401: 41 ldcopr16 r0, r1, AMEVCNTR00 /* index 0 */ 42 bx lr 43 ldcopr16 r0, r1, AMEVCNTR01 /* index 1 */ 44 bx lr 45 ldcopr16 r0, r1, AMEVCNTR02 /* index 2 */ 46 bx lr 47 ldcopr16 r0, r1, AMEVCNTR03 /* index 3 */ 48 bx lr 49endfunc amu_group0_cnt_read_internal 50 51/* 52 * void amu_group0_cnt_write_internal(int idx, uint64_t val); 53 * 54 * Given `idx`, write `val` to the corresponding AMU counter. 55 * `idx` is passed in `r0` and `val` is passed in `r2` and `r3`. 56 * `r1` is used as a scratch register. 57 */ 58func amu_group0_cnt_write_internal 59#if ENABLE_ASSERTIONS 60 /* `idx` should be between [0, 3] */ 61 mov r1, r0 62 lsr r1, r1, #2 63 cmp r1, #0 64 ASM_ASSERT(eq) 65#endif 66 67 /* 68 * Given `idx` calculate address of stcopr16/bx lr instruction pair 69 * in the table below. 70 */ 71 adr r1, 1f 72 lsl r0, r0, #3 /* each stcopr16/bx lr sequence is 8 bytes */ 73 add r1, r1, r0 74 bx r1 75 761: 77 stcopr16 r2, r3, AMEVCNTR00 /* index 0 */ 78 bx lr 79 stcopr16 r2, r3, AMEVCNTR01 /* index 1 */ 80 bx lr 81 stcopr16 r2, r3, AMEVCNTR02 /* index 2 */ 82 bx lr 83 stcopr16 r2, r3, AMEVCNTR03 /* index 3 */ 84 bx lr 85endfunc amu_group0_cnt_write_internal 86 87/* 88 * uint64_t amu_group1_cnt_read_internal(int idx); 89 * 90 * Given `idx`, read the corresponding AMU counter 91 * and return it in `r0` and `r1`. 92 */ 93func amu_group1_cnt_read_internal 94#if ENABLE_ASSERTIONS 95 /* `idx` should be between [0, 15] */ 96 mov r1, r0 97 lsr r1, r1, #4 98 cmp r1, #0 99 ASM_ASSERT(eq) 100#endif 101 102 /* 103 * Given `idx` calculate address of ldcopr16/bx lr instruction pair 104 * in the table below. 105 */ 106 adr r1, 1f 107 lsl r0, r0, #3 /* each ldcopr16/bx lr sequence is 8 bytes */ 108 add r1, r1, r0 109 bx r1 110 1111: 112 ldcopr16 r0, r1, AMEVCNTR10 /* index 0 */ 113 bx lr 114 ldcopr16 r0, r1, AMEVCNTR11 /* index 1 */ 115 bx lr 116 ldcopr16 r0, r1, AMEVCNTR12 /* index 2 */ 117 bx lr 118 ldcopr16 r0, r1, AMEVCNTR13 /* index 3 */ 119 bx lr 120 ldcopr16 r0, r1, AMEVCNTR14 /* index 4 */ 121 bx lr 122 ldcopr16 r0, r1, AMEVCNTR15 /* index 5 */ 123 bx lr 124 ldcopr16 r0, r1, AMEVCNTR16 /* index 6 */ 125 bx lr 126 ldcopr16 r0, r1, AMEVCNTR17 /* index 7 */ 127 bx lr 128 ldcopr16 r0, r1, AMEVCNTR18 /* index 8 */ 129 bx lr 130 ldcopr16 r0, r1, AMEVCNTR19 /* index 9 */ 131 bx lr 132 ldcopr16 r0, r1, AMEVCNTR1A /* index 10 */ 133 bx lr 134 ldcopr16 r0, r1, AMEVCNTR1B /* index 11 */ 135 bx lr 136 ldcopr16 r0, r1, AMEVCNTR1C /* index 12 */ 137 bx lr 138 ldcopr16 r0, r1, AMEVCNTR1D /* index 13 */ 139 bx lr 140 ldcopr16 r0, r1, AMEVCNTR1E /* index 14 */ 141 bx lr 142 ldcopr16 r0, r1, AMEVCNTR1F /* index 15 */ 143 bx lr 144endfunc amu_group1_cnt_read_internal 145 146/* 147 * void amu_group1_cnt_write_internal(int idx, uint64_t val); 148 * 149 * Given `idx`, write `val` to the corresponding AMU counter. 150 * `idx` is passed in `r0` and `val` is passed in `r2` and `r3`. 151 * `r1` is used as a scratch register. 152 */ 153func amu_group1_cnt_write_internal 154#if ENABLE_ASSERTIONS 155 /* `idx` should be between [0, 15] */ 156 mov r1, r0 157 lsr r1, r1, #4 158 cmp r1, #0 159 ASM_ASSERT(eq) 160#endif 161 162 /* 163 * Given `idx` calculate address of ldcopr16/bx lr instruction pair 164 * in the table below. 165 */ 166 adr r1, 1f 167 lsl r0, r0, #3 /* each stcopr16/bx lr sequence is 8 bytes */ 168 add r1, r1, r0 169 bx r1 170 1711: 172 stcopr16 r2, r3, AMEVCNTR10 /* index 0 */ 173 bx lr 174 stcopr16 r2, r3, AMEVCNTR11 /* index 1 */ 175 bx lr 176 stcopr16 r2, r3, AMEVCNTR12 /* index 2 */ 177 bx lr 178 stcopr16 r2, r3, AMEVCNTR13 /* index 3 */ 179 bx lr 180 stcopr16 r2, r3, AMEVCNTR14 /* index 4 */ 181 bx lr 182 stcopr16 r2, r3, AMEVCNTR15 /* index 5 */ 183 bx lr 184 stcopr16 r2, r3, AMEVCNTR16 /* index 6 */ 185 bx lr 186 stcopr16 r2, r3, AMEVCNTR17 /* index 7 */ 187 bx lr 188 stcopr16 r2, r3, AMEVCNTR18 /* index 8 */ 189 bx lr 190 stcopr16 r2, r3, AMEVCNTR19 /* index 9 */ 191 bx lr 192 stcopr16 r2, r3, AMEVCNTR1A /* index 10 */ 193 bx lr 194 stcopr16 r2, r3, AMEVCNTR1B /* index 11 */ 195 bx lr 196 stcopr16 r2, r3, AMEVCNTR1C /* index 12 */ 197 bx lr 198 stcopr16 r2, r3, AMEVCNTR1D /* index 13 */ 199 bx lr 200 stcopr16 r2, r3, AMEVCNTR1E /* index 14 */ 201 bx lr 202 stcopr16 r2, r3, AMEVCNTR1F /* index 15 */ 203 bx lr 204endfunc amu_group1_cnt_write_internal 205 206/* 207 * void amu_group1_set_evtype_internal(int idx, unsigned int val); 208 * 209 * Program the AMU event type register indexed by `idx` 210 * with the value `val`. 211 */ 212func amu_group1_set_evtype_internal 213#if ENABLE_ASSERTIONS 214 /* `idx` should be between [0, 15] */ 215 mov r2, r0 216 lsr r2, r2, #4 217 cmp r2, #0 218 ASM_ASSERT(eq) 219 220 /* val should be between [0, 65535] */ 221 mov r2, r1 222 lsr r2, r2, #16 223 cmp r2, #0 224 ASM_ASSERT(eq) 225#endif 226 227 /* 228 * Given `idx` calculate address of stcopr/bx lr instruction pair 229 * in the table below. 230 */ 231 adr r2, 1f 232 lsl r0, r0, #3 /* each stcopr/bx lr sequence is 8 bytes */ 233 add r2, r2, r0 234 bx r2 235 2361: 237 stcopr r1, AMEVTYPER10 /* index 0 */ 238 bx lr 239 stcopr r1, AMEVTYPER11 /* index 1 */ 240 bx lr 241 stcopr r1, AMEVTYPER12 /* index 2 */ 242 bx lr 243 stcopr r1, AMEVTYPER13 /* index 3 */ 244 bx lr 245 stcopr r1, AMEVTYPER14 /* index 4 */ 246 bx lr 247 stcopr r1, AMEVTYPER15 /* index 5 */ 248 bx lr 249 stcopr r1, AMEVTYPER16 /* index 6 */ 250 bx lr 251 stcopr r1, AMEVTYPER17 /* index 7 */ 252 bx lr 253 stcopr r1, AMEVTYPER18 /* index 8 */ 254 bx lr 255 stcopr r1, AMEVTYPER19 /* index 9 */ 256 bx lr 257 stcopr r1, AMEVTYPER1A /* index 10 */ 258 bx lr 259 stcopr r1, AMEVTYPER1B /* index 11 */ 260 bx lr 261 stcopr r1, AMEVTYPER1C /* index 12 */ 262 bx lr 263 stcopr r1, AMEVTYPER1D /* index 13 */ 264 bx lr 265 stcopr r1, AMEVTYPER1E /* index 14 */ 266 bx lr 267 stcopr r1, AMEVTYPER1F /* index 15 */ 268 bx lr 269endfunc amu_group1_set_evtype_internal 270