1 /*
2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <stdbool.h>
9
10 #include <platform_def.h>
11
12 #include <arch.h>
13 #include <arch_features.h>
14 #include <arch_helpers.h>
15 #include <lib/cassert.h>
16 #include <lib/utils_def.h>
17 #include <lib/xlat_tables/xlat_tables_v2.h>
18
19 #include "../xlat_tables_private.h"
20
21 #if (ARM_ARCH_MAJOR == 7) && !defined(ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING)
22 #error ARMv7 target does not support LPAE MMU descriptors
23 #endif
24
25 /*
26 * Returns true if the provided granule size is supported, false otherwise.
27 */
xlat_arch_is_granule_size_supported(size_t size)28 bool xlat_arch_is_granule_size_supported(size_t size)
29 {
30 /*
31 * The library uses the long descriptor translation table format, which
32 * supports 4 KiB pages only.
33 */
34 return size == PAGE_SIZE_4KB;
35 }
36
xlat_arch_get_max_supported_granule_size(void)37 size_t xlat_arch_get_max_supported_granule_size(void)
38 {
39 return PAGE_SIZE_4KB;
40 }
41
42 #if ENABLE_ASSERTIONS
xlat_arch_get_max_supported_pa(void)43 unsigned long long xlat_arch_get_max_supported_pa(void)
44 {
45 /* Physical address space size for long descriptor format. */
46 return (1ULL << 40) - 1ULL;
47 }
48
49 /*
50 * Return minimum virtual address space size supported by the architecture
51 */
xlat_get_min_virt_addr_space_size(void)52 uintptr_t xlat_get_min_virt_addr_space_size(void)
53 {
54 return MIN_VIRT_ADDR_SPACE_SIZE;
55 }
56 #endif /* ENABLE_ASSERTIONS*/
57
is_mmu_enabled_ctx(const xlat_ctx_t * ctx)58 bool is_mmu_enabled_ctx(const xlat_ctx_t *ctx)
59 {
60 if (ctx->xlat_regime == EL1_EL0_REGIME) {
61 assert(xlat_arch_current_el() == 1U);
62 return (read_sctlr() & SCTLR_M_BIT) != 0U;
63 } else {
64 assert(ctx->xlat_regime == EL2_REGIME);
65 assert(xlat_arch_current_el() == 2U);
66 return (read_hsctlr() & HSCTLR_M_BIT) != 0U;
67 }
68 }
69
is_dcache_enabled(void)70 bool is_dcache_enabled(void)
71 {
72 if (IS_IN_EL2()) {
73 return (read_hsctlr() & HSCTLR_C_BIT) != 0U;
74 } else {
75 return (read_sctlr() & SCTLR_C_BIT) != 0U;
76 }
77 }
78
xlat_arch_regime_get_xn_desc(int xlat_regime)79 uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime)
80 {
81 if (xlat_regime == EL1_EL0_REGIME) {
82 return UPPER_ATTRS(XN) | UPPER_ATTRS(PXN);
83 } else {
84 assert(xlat_regime == EL2_REGIME);
85 return UPPER_ATTRS(XN);
86 }
87 }
88
xlat_arch_tlbi_va(uintptr_t va,int xlat_regime)89 void xlat_arch_tlbi_va(uintptr_t va, int xlat_regime)
90 {
91 /*
92 * Ensure the translation table write has drained into memory before
93 * invalidating the TLB entry.
94 */
95 dsbishst();
96
97 if (xlat_regime == EL1_EL0_REGIME) {
98 tlbimvaais(TLBI_ADDR(va));
99 } else {
100 assert(xlat_regime == EL2_REGIME);
101 tlbimvahis(TLBI_ADDR(va));
102 }
103 }
104
xlat_arch_tlbi_va_sync(void)105 void xlat_arch_tlbi_va_sync(void)
106 {
107 /* Invalidate all entries from branch predictors. */
108 bpiallis();
109
110 /*
111 * A TLB maintenance instruction can complete at any time after
112 * it is issued, but is only guaranteed to be complete after the
113 * execution of DSB by the PE that executed the TLB maintenance
114 * instruction. After the TLB invalidate instruction is
115 * complete, no new memory accesses using the invalidated TLB
116 * entries will be observed by any observer of the system
117 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph
118 * "Ordering and completion of TLB maintenance instructions".
119 */
120 dsbish();
121
122 /*
123 * The effects of a completed TLB maintenance instruction are
124 * only guaranteed to be visible on the PE that executed the
125 * instruction after the execution of an ISB instruction by the
126 * PE that executed the TLB maintenance instruction.
127 */
128 isb();
129 }
130
xlat_arch_current_el(void)131 unsigned int xlat_arch_current_el(void)
132 {
133 if (IS_IN_HYP()) {
134 return 2U;
135 } else {
136 assert(IS_IN_SVC() || IS_IN_MON());
137 /*
138 * If EL3 is in AArch32 mode, all secure PL1 modes (Monitor,
139 * System, SVC, Abort, UND, IRQ and FIQ modes) execute at EL3.
140 *
141 * The PL1&0 translation regime in AArch32 behaves like the
142 * EL1&0 regime in AArch64 except for the XN bits, but we set
143 * and unset them at the same time, so there's no difference in
144 * practice.
145 */
146 return 1U;
147 }
148 }
149
150 /*******************************************************************************
151 * Function for enabling the MMU in PL1 or PL2, assuming that the page tables
152 * have already been created.
153 ******************************************************************************/
setup_mmu_cfg(uint64_t * params,unsigned int flags,const uint64_t * base_table,unsigned long long max_pa,uintptr_t max_va,__unused int xlat_regime)154 void setup_mmu_cfg(uint64_t *params, unsigned int flags,
155 const uint64_t *base_table, unsigned long long max_pa,
156 uintptr_t max_va, __unused int xlat_regime)
157 {
158 uint64_t mair, ttbr0;
159 uint32_t ttbcr;
160
161 /* Set attributes in the right indices of the MAIR */
162 mair = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);
163 mair |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR,
164 ATTR_IWBWA_OWBWA_NTR_INDEX);
165 mair |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE,
166 ATTR_NON_CACHEABLE_INDEX);
167
168 /*
169 * Configure the control register for stage 1 of the PL1&0 or EL2
170 * translation regimes.
171 */
172
173 /* Use the Long-descriptor translation table format. */
174 ttbcr = TTBCR_EAE_BIT;
175
176 if (xlat_regime == EL1_EL0_REGIME) {
177 assert(IS_IN_SVC() || IS_IN_MON());
178 /*
179 * Disable translation table walk for addresses that are
180 * translated using TTBR1. Therefore, only TTBR0 is used.
181 */
182 ttbcr |= TTBCR_EPD1_BIT;
183 } else {
184 assert(xlat_regime == EL2_REGIME);
185 assert(IS_IN_HYP());
186
187 /*
188 * Set HTCR bits as well. Set HTTBR table properties
189 * as Inner & outer WBWA & shareable.
190 */
191 ttbcr |= HTCR_RES1 |
192 HTCR_SH0_INNER_SHAREABLE | HTCR_RGN0_OUTER_WBA |
193 HTCR_RGN0_INNER_WBA;
194 }
195
196 /*
197 * Limit the input address ranges and memory region sizes translated
198 * using TTBR0 to the given virtual address space size, if smaller than
199 * 32 bits.
200 */
201 if (max_va != UINT32_MAX) {
202 uintptr_t virtual_addr_space_size = max_va + 1U;
203
204 assert(virtual_addr_space_size >=
205 xlat_get_min_virt_addr_space_size());
206 assert(virtual_addr_space_size <=
207 MAX_VIRT_ADDR_SPACE_SIZE);
208 assert(IS_POWER_OF_TWO(virtual_addr_space_size));
209
210 /*
211 * __builtin_ctzll(0) is undefined but here we are guaranteed
212 * that virtual_addr_space_size is in the range [1, UINT32_MAX].
213 */
214 int t0sz = 32 - __builtin_ctzll(virtual_addr_space_size);
215
216 ttbcr |= (uint32_t) t0sz;
217 }
218
219 /*
220 * Set the cacheability and shareability attributes for memory
221 * associated with translation table walks using TTBR0.
222 */
223 if ((flags & XLAT_TABLE_NC) != 0U) {
224 /* Inner & outer non-cacheable non-shareable. */
225 ttbcr |= TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC |
226 TTBCR_RGN0_INNER_NC;
227 } else {
228 /* Inner & outer WBWA & shareable. */
229 ttbcr |= TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA |
230 TTBCR_RGN0_INNER_WBA;
231 }
232
233 /* Set TTBR0 bits as well */
234 ttbr0 = (uint64_t)(uintptr_t) base_table;
235
236 if (is_armv8_2_ttcnp_present()) {
237 /* Enable CnP bit so as to share page tables with all PEs. */
238 ttbr0 |= TTBR_CNP_BIT;
239 }
240
241 /* Now populate MMU configuration */
242 params[MMU_CFG_MAIR] = mair;
243 params[MMU_CFG_TCR] = (uint64_t) ttbcr;
244 params[MMU_CFG_TTBR0] = ttbr0;
245 }
246