1 /* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <lib/utils_def.h> 12 #include <plat/common/common_def.h> 13 14 #include <sunxi_mmap.h> 15 16 #define BL31_BASE SUNXI_SRAM_A2_BASE 17 #define BL31_LIMIT (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE) 18 19 /* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */ 20 #define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000) 21 #define BL31_NOBITS_LIMIT (SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE) 22 23 /* The traditional U-Boot load address is 160MB into DRAM, so at 0x4a000000 */ 24 #define PLAT_SUNXI_NS_IMAGE_OFFSET (SUNXI_DRAM_BASE + (160U << 20)) 25 26 /* How much memory to reserve as secure for BL32, if configured */ 27 #define SUNXI_DRAM_SEC_SIZE (32U << 20) 28 29 /* How much DRAM to map (to map BL33, for fetching the DTB from U-Boot) */ 30 #define SUNXI_DRAM_MAP_SIZE (64U << 20) 31 32 #define CACHE_WRITEBACK_SHIFT 6 33 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 34 35 #define MAX_MMAP_REGIONS (3 + PLATFORM_MMAP_REGIONS) 36 #define MAX_XLAT_TABLES 1 37 38 #define PLAT_MAX_PWR_LVL_STATES U(2) 39 #define PLAT_MAX_RET_STATE U(1) 40 #define PLAT_MAX_OFF_STATE U(2) 41 42 #define PLAT_MAX_PWR_LVL U(2) 43 #define PLAT_NUM_PWR_DOMAINS (U(1) + \ 44 PLATFORM_CLUSTER_COUNT + \ 45 PLATFORM_CORE_COUNT) 46 47 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 48 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28) 49 50 #define PLATFORM_CLUSTER_COUNT U(1) 51 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 52 PLATFORM_MAX_CPUS_PER_CLUSTER) 53 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 54 #define PLATFORM_MMAP_REGIONS 4 55 #define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT) 56 57 #ifndef SPD_none 58 #ifndef BL32_BASE 59 #define BL32_BASE SUNXI_DRAM_BASE 60 #endif 61 #endif 62 63 #endif /* PLATFORM_DEF_H */ 64