1 /* 2 * Copyright (c) 2019-2020, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <lib/utils_def.h> 12 #include <lib/xlat_tables/xlat_tables_defs.h> 13 #include <plat/arm/board/common/v2m_def.h> 14 #include <plat/common/common_def.h> 15 16 /* Memory location options for TSP */ 17 #define ARM_DRAM_ID 2 18 19 #define ARM_DRAM1_BASE UL(0x80000000) 20 #define ARM_DRAM1_SIZE UL(0x80000000) 21 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 22 ARM_DRAM1_SIZE - 1) 23 24 #define SRAM_BASE 0x2000000 25 #define SRAM_SIZE 0x200000 26 27 /* The first 4KB of NS DRAM1 are used as shared memory */ 28 #define A5DS_SHARED_RAM_BASE SRAM_BASE 29 #define A5DS_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 30 31 /* The next 252 kB of NS DRAM is used to load the BL images */ 32 #define ARM_BL_RAM_BASE (A5DS_SHARED_RAM_BASE + \ 33 A5DS_SHARED_RAM_SIZE) 34 #define ARM_BL_RAM_SIZE (PLAT_ARM_BL_PLUS_SHARED_RAM_SIZE - \ 35 A5DS_SHARED_RAM_SIZE) 36 37 #define PERIPHBASE 0x1a000000 38 #define PERIPH_SIZE 0x00240000 39 #define A5_PERIPHERALS_BASE 0x1c000000 40 #define A5_PERIPHERALS_SIZE 0x10000 41 42 #define ARM_CACHE_WRITEBACK_SHIFT 5 43 44 #define ARM_IRQ_SEC_PHY_TIMER 29 45 46 #define ARM_IRQ_SEC_SGI_0 8 47 #define ARM_IRQ_SEC_SGI_1 9 48 #define ARM_IRQ_SEC_SGI_2 10 49 #define ARM_IRQ_SEC_SGI_3 11 50 #define ARM_IRQ_SEC_SGI_4 12 51 #define ARM_IRQ_SEC_SGI_5 13 52 #define ARM_IRQ_SEC_SGI_6 14 53 #define ARM_IRQ_SEC_SGI_7 15 54 55 /* 56 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 57 * terminology. On a GICv2 system or mode, the lists will be merged and treated 58 * as Group 0 interrupts. 59 */ 60 #define ARM_G1S_IRQ_PROPS(grp) \ 61 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 62 GIC_INTR_CFG_LEVEL), \ 63 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 64 GIC_INTR_CFG_EDGE), \ 65 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 66 GIC_INTR_CFG_EDGE), \ 67 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 68 GIC_INTR_CFG_EDGE), \ 69 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 70 GIC_INTR_CFG_EDGE), \ 71 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 72 GIC_INTR_CFG_EDGE), \ 73 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 74 GIC_INTR_CFG_EDGE) 75 76 #define ARM_G0_IRQ_PROPS(grp) \ 77 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 78 GIC_INTR_CFG_EDGE) 79 80 #define A5DS_IRQ_TZ_WDOG 56 81 #define A5DS_IRQ_SEC_SYS_TIMER 57 82 83 /* Default cluster count for A5DS */ 84 #define A5DS_CLUSTER_COUNT U(1) 85 86 /* Default number of CPUs per cluster on A5DS */ 87 #define A5DS_MAX_CPUS_PER_CLUSTER U(4) 88 89 /* Default number of threads per CPU on A5DS */ 90 #define A5DS_MAX_PE_PER_CPU U(1) 91 92 #define A5DS_CORE_COUNT U(4) 93 94 #define A5DS_PRIMARY_CPU 0x0 95 96 #define BOOT_BASE ARM_DRAM1_BASE 97 #define BOOT_SIZE UL(0x2800000) 98 99 #define ARM_NS_DRAM1_BASE (ARM_DRAM1_BASE + BOOT_SIZE) 100 /* 101 * The last 2MB is meant to be NOLOAD and will not be zero 102 * initialized. 103 */ 104 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 105 BOOT_SIZE - \ 106 0x00200000) 107 108 #define MAP_BOOT_RW MAP_REGION_FLAT( \ 109 BOOT_BASE, \ 110 BOOT_SIZE, \ 111 MT_DEVICE | MT_RW | MT_SECURE) 112 113 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 114 A5DS_SHARED_RAM_BASE, \ 115 A5DS_SHARED_RAM_SIZE, \ 116 MT_MEMORY | MT_RW | MT_SECURE) 117 118 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 119 ARM_NS_DRAM1_BASE, \ 120 ARM_NS_DRAM1_SIZE, \ 121 MT_MEMORY | MT_RW | MT_NS) 122 123 #define ARM_MAP_SRAM MAP_REGION_FLAT( \ 124 SRAM_BASE, \ 125 SRAM_SIZE, \ 126 MT_MEMORY | MT_RW | MT_NS) 127 128 /* 129 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to 130 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides 131 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order 132 * to be able to access the heap. 133 */ 134 135 #define ARM_MAP_BL_RO MAP_REGION_FLAT(\ 136 BL_CODE_BASE,\ 137 BL_CODE_END - BL_CODE_BASE,\ 138 MT_CODE | MT_SECURE),\ 139 MAP_REGION_FLAT(\ 140 BL_RO_DATA_BASE,\ 141 BL_RO_DATA_END\ 142 - BL_RO_DATA_BASE, \ 143 MT_RO_DATA | MT_SECURE) 144 145 #if USE_COHERENT_MEM 146 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT(\ 147 BL_COHERENT_RAM_BASE,\ 148 BL_COHERENT_RAM_END \ 149 - BL_COHERENT_RAM_BASE, \ 150 MT_DEVICE | MT_RW | MT_SECURE) 151 #endif 152 153 /* 154 * The max number of regions like RO(code), coherent and data required by 155 * different BL stages which need to be mapped in the MMU. 156 */ 157 #define ARM_BL_REGIONS 5 158 159 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 160 ARM_BL_REGIONS) 161 162 /* Memory mapped Generic timer interfaces */ 163 #define A5DS_TIMER_BASE_FREQUENCY UL(7500000) 164 165 #define ARM_CONSOLE_BAUDRATE 115200 166 167 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 168 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 169 170 /* 171 * This macro defines the deepest retention state possible. A higher state 172 * id will represent an invalid or a power down state. 173 */ 174 #define PLAT_MAX_RET_STATE 1 175 176 /* 177 * This macro defines the deepest power down states possible. Any state ID 178 * higher than this is invalid. 179 */ 180 #define PLAT_MAX_OFF_STATE 2 181 182 /* 183 * Some data must be aligned on the biggest cache line size in the platform. 184 * This is known only to the platform as it might have a combination of 185 * integrated and external caches. 186 */ 187 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 188 189 /* 190 * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base 191 * and limit. Leave enough space of BL2 meminfo. 192 */ 193 #define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 194 #define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE) 195 196 /******************************************************************************* 197 * BL1 specific defines. 198 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 199 * addresses. 200 ******************************************************************************/ 201 #define BL1_RO_BASE 0x00000000 202 #define BL1_RO_LIMIT PLAT_ARM_TRUSTED_ROM_SIZE 203 /* 204 * Put BL1 RW at the top of the memory allocated for BL images in NS DRAM. 205 */ 206 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 207 ARM_BL_RAM_SIZE - \ 208 (PLAT_ARM_MAX_BL1_RW_SIZE)) 209 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 210 (ARM_BL_RAM_SIZE)) 211 /******************************************************************************* 212 * BL2 specific defines. 213 ******************************************************************************/ 214 215 /* 216 * Put BL2 just below BL1. 217 */ 218 #define BL2_BASE (BL1_RW_BASE - A5DS_MAX_BL2_SIZE) 219 #define BL2_LIMIT BL1_RW_BASE 220 221 /* Put BL32 below BL2 in NS DRAM.*/ 222 #define ARM_BL2_MEM_DESC_BASE ARM_TB_FW_CONFIG_LIMIT 223 224 #define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 225 - PLAT_ARM_MAX_BL32_SIZE) 226 #define BL32_PROGBITS_LIMIT BL2_BASE 227 #define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 228 229 /* Required platform porting definitions */ 230 #define PLATFORM_CORE_COUNT A5DS_CORE_COUNT 231 #define PLAT_NUM_PWR_DOMAINS (A5DS_CLUSTER_COUNT + \ 232 PLATFORM_CORE_COUNT) + U(1) 233 234 #define PLAT_MAX_PWR_LVL 2 235 236 /* 237 * Other platform porting definitions are provided by included headers 238 */ 239 240 /* 241 * Required ARM standard platform porting definitions 242 */ 243 244 #define PLAT_ARM_BL_PLUS_SHARED_RAM_SIZE 0x00040000 /* 256 KB */ 245 246 #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 247 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x10000 /* 64KB */ 248 249 #define PLAT_ARM_DRAM2_SIZE ULL(0x80000000) 250 251 /* 252 * Load address of BL33 for this platform port 253 */ 254 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + U(0x8000000)) 255 256 /* 257 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 258 * plat_arm_mmap array defined for each BL stage. 259 */ 260 #if defined(IMAGE_BL32) 261 # define PLAT_ARM_MMAP_ENTRIES 8 262 # define MAX_XLAT_TABLES 6 263 #else 264 # define PLAT_ARM_MMAP_ENTRIES 12 265 # define MAX_XLAT_TABLES 6 266 #endif 267 268 /* 269 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 270 * plus a little space for growth. 271 */ 272 #define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000 273 274 /* 275 * A5DS_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 276 * little space for growth. 277 */ 278 #define A5DS_MAX_BL2_SIZE 0x11000 279 280 /* 281 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 282 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 283 * BL2 and BL1-RW 284 */ 285 #define PLAT_ARM_MAX_BL32_SIZE 0x3B000 286 /* 287 * Size of cacheable stacks 288 */ 289 #if defined(IMAGE_BL1) 290 # define PLATFORM_STACK_SIZE 0x440 291 #elif defined(IMAGE_BL2) 292 # define PLATFORM_STACK_SIZE 0x400 293 #elif defined(IMAGE_BL32) 294 # define PLATFORM_STACK_SIZE 0x440 295 #endif 296 297 #define MAX_IO_DEVICES 3 298 #define MAX_IO_HANDLES 4 299 300 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 301 #define PLAT_ARM_FIP_BASE BOOT_BASE 302 #define PLAT_ARM_FIP_MAX_SIZE (BOOT_SIZE - V2M_FLASH_BLOCK_SIZE) 303 304 #define PLAT_ARM_NVM_BASE BOOT_BASE 305 #define PLAT_ARM_NVM_SIZE (BOOT_SIZE - V2M_FLASH_BLOCK_SIZE) 306 307 /* 308 * PL011 related constants 309 */ 310 #define PLAT_ARM_BOOT_UART_BASE 0x1A200000 311 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ UL(7500000) 312 313 #define PLAT_ARM_RUN_UART_BASE 0x1A210000 314 #define PLAT_ARM_RUN_UART_CLK_IN_HZ UL(7500000) 315 316 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 317 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 318 319 #define A5DS_TIMER_BASE_FREQUENCY UL(7500000) 320 321 /* System timer related constants */ 322 #define PLAT_ARM_NSTIMER_FRAME_ID 1 323 324 /* Mailbox base address */ 325 #define A5DS_TRUSTED_MAILBOX_BASE A5DS_SHARED_RAM_BASE 326 #define A5DS_TRUSTED_MAILBOX_SIZE (8 + A5DS_HOLD_SIZE) 327 #define A5DS_HOLD_BASE (A5DS_TRUSTED_MAILBOX_BASE + 8) 328 #define A5DS_HOLD_SIZE (PLATFORM_CORE_COUNT * \ 329 A5DS_HOLD_ENTRY_SIZE) 330 #define A5DS_HOLD_ENTRY_SHIFT 3 331 #define A5DS_HOLD_ENTRY_SIZE (1 << A5DS_HOLD_ENTRY_SHIFT) 332 #define A5DS_HOLD_STATE_WAIT 0 333 #define A5DS_HOLD_STATE_GO 1 334 335 /* Snoop Control Unit base address */ 336 #define A5DS_SCU_BASE 0x1C000000 337 338 /* 339 * GIC related constants to cater for GICv2 340 */ 341 #define PLAT_ARM_GICD_BASE 0x1C001000 342 #define PLAT_ARM_GICC_BASE 0x1C000100 343 344 /* 345 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 346 * terminology. On a GICv2 system or mode, the lists will be merged and treated 347 * as Group 0 interrupts. 348 */ 349 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 350 ARM_G1S_IRQ_PROPS(grp), \ 351 INTR_PROP_DESC(A5DS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 352 GIC_INTR_CFG_LEVEL), \ 353 INTR_PROP_DESC(A5DS_IRQ_SEC_SYS_TIMER,\ 354 GIC_HIGHEST_SEC_PRIORITY, (grp), \ 355 GIC_INTR_CFG_LEVEL) 356 357 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 358 359 #endif /* PLATFORM_DEF_H */ 360