1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <platform_def.h> 8 #include <plat/arm/common/plat_arm.h> 9 10 /* 11 * Table of memory regions for different BL stages to map using the MMU. 12 * This doesn't include Trusted SRAM as setup_page_tables() already takes care 13 * of mapping it. 14 */ 15 #ifdef IMAGE_BL1 16 const mmap_region_t plat_arm_mmap[] = { 17 ARM_MAP_SHARED_RAM, 18 V2M_MAP_FLASH0_RW, 19 V2M_MAP_IOFPGA, 20 CSS_MAP_DEVICE, 21 SOC_CSS_MAP_DEVICE, 22 #if TRUSTED_BOARD_BOOT 23 /* Map DRAM to authenticate NS_BL2U image. */ 24 ARM_MAP_NS_DRAM1, 25 #endif 26 {0} 27 }; 28 #endif 29 #ifdef IMAGE_BL2 30 const mmap_region_t plat_arm_mmap[] = { 31 ARM_MAP_SHARED_RAM, 32 V2M_MAP_FLASH0_RW, 33 #ifdef PLAT_ARM_MEM_PROT_ADDR 34 ARM_V2M_MAP_MEM_PROTECT, 35 #endif 36 V2M_MAP_IOFPGA, 37 CSS_MAP_DEVICE, 38 SOC_CSS_MAP_DEVICE, 39 ARM_MAP_NS_DRAM1, 40 #ifdef __aarch64__ 41 ARM_MAP_DRAM2, 42 #endif 43 #ifdef SPD_tspd 44 ARM_MAP_TSP_SEC_MEM, 45 #endif 46 #ifdef SPD_opteed 47 ARM_MAP_OPTEE_CORE_MEM, 48 ARM_OPTEE_PAGEABLE_LOAD_MEM, 49 #endif 50 #if TRUSTED_BOARD_BOOT && !BL2_AT_EL3 51 ARM_MAP_BL1_RW, 52 #endif 53 {0} 54 }; 55 #endif 56 #ifdef IMAGE_BL2U 57 const mmap_region_t plat_arm_mmap[] = { 58 ARM_MAP_SHARED_RAM, 59 CSS_MAP_DEVICE, 60 CSS_MAP_SCP_BL2U, 61 V2M_MAP_IOFPGA, 62 SOC_CSS_MAP_DEVICE, 63 {0} 64 }; 65 #endif 66 #ifdef IMAGE_BL31 67 const mmap_region_t plat_arm_mmap[] = { 68 ARM_MAP_SHARED_RAM, 69 V2M_MAP_IOFPGA, 70 CSS_MAP_DEVICE, 71 #ifdef PLAT_ARM_MEM_PROT_ADDR 72 ARM_V2M_MAP_MEM_PROTECT, 73 #endif 74 SOC_CSS_MAP_DEVICE, 75 {0} 76 }; 77 #endif 78 #ifdef IMAGE_BL32 79 const mmap_region_t plat_arm_mmap[] = { 80 #ifndef __aarch64__ 81 ARM_MAP_SHARED_RAM, 82 #ifdef PLAT_ARM_MEM_PROT_ADDR 83 ARM_V2M_MAP_MEM_PROTECT, 84 #endif 85 #endif 86 V2M_MAP_IOFPGA, 87 CSS_MAP_DEVICE, 88 SOC_CSS_MAP_DEVICE, 89 {0} 90 }; 91 #endif 92 93 ARM_CASSERT_MMAP 94