1 /*
2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <drivers/arm/ccn.h>
14 #include <plat/arm/common/plat_arm.h>
15 #include <plat/common/platform.h>
16 #include <drivers/arm/sbsa.h>
17 #include <sgi_base_platform_def.h>
18 #include <services/spm_mm_partition.h>
19
20 #define SGI_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
21 V2M_FLASH0_SIZE, \
22 MT_DEVICE | MT_RO | MT_SECURE)
23 /*
24 * Table of regions for different BL stages to map using the MMU.
25 * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
26 * arm_configure_mmu_elx() will give the available subset of that.
27 *
28 * Replace or extend the below regions as required
29 */
30 #if IMAGE_BL1
31 const mmap_region_t plat_arm_mmap[] = {
32 ARM_MAP_SHARED_RAM,
33 SGI_MAP_FLASH0_RO,
34 CSS_SGI_MAP_DEVICE,
35 SOC_CSS_MAP_DEVICE,
36 {0}
37 };
38 #endif
39 #if IMAGE_BL2
40 const mmap_region_t plat_arm_mmap[] = {
41 ARM_MAP_SHARED_RAM,
42 SGI_MAP_FLASH0_RO,
43 CSS_SGI_MAP_DEVICE,
44 SOC_CSS_MAP_DEVICE,
45 ARM_MAP_NS_DRAM1,
46 #if ARM_BL31_IN_DRAM
47 ARM_MAP_BL31_SEC_DRAM,
48 #endif
49 #if SPM_MM
50 ARM_SP_IMAGE_MMAP,
51 #endif
52 #if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
53 ARM_MAP_BL1_RW,
54 #endif
55 {0}
56 };
57 #endif
58 #if IMAGE_BL31
59 const mmap_region_t plat_arm_mmap[] = {
60 ARM_MAP_SHARED_RAM,
61 V2M_MAP_IOFPGA,
62 CSS_SGI_MAP_DEVICE,
63 SOC_CSS_MAP_DEVICE,
64 #if SPM_MM
65 ARM_SPM_BUF_EL3_MMAP,
66 #endif
67 {0}
68 };
69
70 #if SPM_MM && defined(IMAGE_BL31)
71 const mmap_region_t plat_arm_secure_partition_mmap[] = {
72 PLAT_ARM_SECURE_MAP_DEVICE,
73 ARM_SP_IMAGE_MMAP,
74 ARM_SP_IMAGE_NS_BUF_MMAP,
75 ARM_SP_CPER_BUF_MMAP,
76 ARM_SP_IMAGE_RW_MMAP,
77 ARM_SPM_BUF_EL0_MMAP,
78 {0}
79 };
80 #endif /* SPM_MM && defined(IMAGE_BL31) */
81 #endif
82
83 ARM_CASSERT_MMAP
84
85 #if SPM_MM && defined(IMAGE_BL31)
86 /*
87 * Boot information passed to a secure partition during initialisation. Linear
88 * indices in MP information will be filled at runtime.
89 */
90 static spm_mm_mp_info_t sp_mp_info[] = {
91 [0] = {0x81000000, 0},
92 [1] = {0x81000100, 0},
93 [2] = {0x81000200, 0},
94 [3] = {0x81000300, 0},
95 [4] = {0x81010000, 0},
96 [5] = {0x81010100, 0},
97 [6] = {0x81010200, 0},
98 [7] = {0x81010300, 0},
99 };
100
101 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
102 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
103 .h.version = VERSION_1,
104 .h.size = sizeof(spm_mm_boot_info_t),
105 .h.attr = 0,
106 .sp_mem_base = ARM_SP_IMAGE_BASE,
107 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
108 .sp_image_base = ARM_SP_IMAGE_BASE,
109 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
110 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
111 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
112 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
113 .sp_image_size = ARM_SP_IMAGE_SIZE,
114 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
115 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
116 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
117 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
118 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
119 .num_cpus = PLATFORM_CORE_COUNT,
120 .mp_info = &sp_mp_info[0],
121 };
122
plat_get_secure_partition_mmap(void * cookie)123 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
124 {
125 return plat_arm_secure_partition_mmap;
126 }
127
plat_get_secure_partition_boot_info(void * cookie)128 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
129 void *cookie)
130 {
131 return &plat_arm_secure_partition_boot_info;
132 }
133 #endif /* SPM_MM && defined(IMAGE_BL31) */
134
135 #if TRUSTED_BOARD_BOOT
plat_get_mbedtls_heap(void ** heap_addr,size_t * heap_size)136 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
137 {
138 assert(heap_addr != NULL);
139 assert(heap_size != NULL);
140
141 return arm_get_mbedtls_heap(heap_addr, heap_size);
142 }
143 #endif
144
plat_arm_secure_wdt_start(void)145 void plat_arm_secure_wdt_start(void)
146 {
147 sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
148 }
149
plat_arm_secure_wdt_stop(void)150 void plat_arm_secure_wdt_stop(void)
151 {
152 sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
153 }
154