1 /*
2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9 #include <string.h>
10
11 #include <platform_def.h>
12
13 #include <arch_helpers.h>
14 #include <common/bl_common.h>
15 #include <common/debug.h>
16 #include <common/tbbr/tbbr_img_def.h>
17 #include <drivers/arm/pl011.h>
18 #include <drivers/arm/pl061_gpio.h>
19 #include <drivers/generic_delay_timer.h>
20 #include <drivers/mmc.h>
21 #include <drivers/synopsys/dw_mmc.h>
22 #include <lib/mmio.h>
23 #include <plat/common/platform.h>
24
25 #include "hi3798cv200.h"
26 #include "plat_private.h"
27
28 /* Data structure which holds the extents of the trusted RAM for BL1 */
29 static meminfo_t bl1_tzram_layout;
30 static meminfo_t bl2_tzram_layout;
31 static console_pl011_t console;
32
33 /*
34 * Cannot use default weak implementation in bl1_main.c because BL1 RW data is
35 * not at the top of the secure memory.
36 */
bl1_plat_handle_post_image_load(unsigned int image_id)37 int bl1_plat_handle_post_image_load(unsigned int image_id)
38 {
39 image_desc_t *image_desc;
40 entry_point_info_t *ep_info;
41
42 if (image_id != BL2_IMAGE_ID)
43 return 0;
44
45 /* Get the image descriptor */
46 image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
47 assert(image_desc != NULL);
48
49 /* Get the entry point info */
50 ep_info = &image_desc->ep_info;
51
52 bl2_tzram_layout.total_base = BL2_BASE;
53 bl2_tzram_layout.total_size = BL32_LIMIT - BL2_BASE;
54
55 flush_dcache_range((uintptr_t)&bl2_tzram_layout, sizeof(meminfo_t));
56
57 ep_info->args.arg1 = (uintptr_t)&bl2_tzram_layout;
58
59 VERBOSE("BL1: BL2 memory layout address = %p\n",
60 (void *)&bl2_tzram_layout);
61
62 return 0;
63 }
64
bl1_early_platform_setup(void)65 void bl1_early_platform_setup(void)
66 {
67 /* Initialize the console to provide early debug support */
68 console_pl011_register(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ,
69 PL011_BAUDRATE, &console);
70
71 /* Allow BL1 to see the whole Trusted RAM */
72 bl1_tzram_layout.total_base = BL1_RW_BASE;
73 bl1_tzram_layout.total_size = BL1_RW_SIZE;
74
75 INFO("BL1: 0x%lx - 0x%lx [size = %zu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
76 BL1_RAM_LIMIT - BL1_RAM_BASE);
77 }
78
bl1_plat_arch_setup(void)79 void bl1_plat_arch_setup(void)
80 {
81 plat_configure_mmu_el3(bl1_tzram_layout.total_base,
82 bl1_tzram_layout.total_size,
83 BL1_RO_BASE, /* l-loader and BL1 ROM */
84 BL1_RO_LIMIT,
85 BL_COHERENT_RAM_BASE,
86 BL_COHERENT_RAM_END);
87 }
88
bl1_platform_setup(void)89 void bl1_platform_setup(void)
90 {
91 int i;
92 #if !POPLAR_RECOVERY
93 struct mmc_device_info info;
94 dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE);
95 #endif
96
97 generic_delay_timer_init();
98
99 pl061_gpio_init();
100 for (i = 0; i < GPIO_MAX; i++)
101 pl061_gpio_register(GPIO_BASE(i), i);
102
103 #if !POPLAR_RECOVERY
104 /* SoC-specific emmc register are initialized/configured by bootrom */
105 INFO("BL1: initializing emmc\n");
106 info.mmc_dev_type = MMC_IS_EMMC;
107 dw_mmc_init(¶ms, &info);
108 #endif
109
110 plat_io_setup();
111 }
112
bl1_plat_get_next_image_id(void)113 unsigned int bl1_plat_get_next_image_id(void)
114 {
115 return BL2_IMAGE_ID;
116 }
117