1 /*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2019, Intel Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <arch.h>
9 #include <arch_helpers.h>
10 #include <assert.h>
11 #include <common/bl_common.h>
12 #include <drivers/arm/gicv2.h>
13 #include <drivers/ti/uart/uart_16550.h>
14 #include <lib/xlat_tables/xlat_tables.h>
15
16
17 static entry_point_info_t bl32_image_ep_info;
18 static entry_point_info_t bl33_image_ep_info;
19
bl31_plat_get_next_image_ep_info(uint32_t type)20 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
21 {
22 entry_point_info_t *next_image_info;
23
24 next_image_info = (type == NON_SECURE) ?
25 &bl33_image_ep_info : &bl32_image_ep_info;
26
27 /* None of the images on this platform can have 0x0 as the entrypoint */
28 if (next_image_info->pc)
29 return next_image_info;
30 else
31 return NULL;
32 }
33
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)34 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
35 u_register_t arg2, u_register_t arg3)
36 {
37 static console_16550_t console;
38
39 console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
40 &console);
41 /*
42 * Check params passed from BL31 should not be NULL,
43 */
44 void *from_bl2 = (void *) arg0;
45
46 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
47
48 assert(params_from_bl2 != NULL);
49 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
50 assert(params_from_bl2->h.version >= VERSION_2);
51
52 /*
53 * Copy BL32 (if populated by BL31) and BL33 entry point information.
54 * They are stored in Secure RAM, in BL31's address space.
55 */
56
57 bl_params_node_t *bl_params = params_from_bl2->head;
58
59 while (bl_params) {
60 if (bl_params->image_id == BL33_IMAGE_ID)
61 bl33_image_ep_info = *bl_params->ep_info;
62
63 bl_params = bl_params->next_params_info;
64 }
65 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
66 }
67
68 static const interrupt_prop_t s10_interrupt_props[] = {
69 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
70 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
71 };
72
73 static unsigned int target_mask_array[PLATFORM_CORE_COUNT];
74
75 static const gicv2_driver_data_t plat_gicv2_gic_data = {
76 .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE,
77 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE,
78 .interrupt_props = s10_interrupt_props,
79 .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props),
80 .target_masks = target_mask_array,
81 .target_masks_num = ARRAY_SIZE(target_mask_array),
82 };
83
84 /*******************************************************************************
85 * Perform any BL3-1 platform setup code
86 ******************************************************************************/
bl31_platform_setup(void)87 void bl31_platform_setup(void)
88 {
89 /* Initialize the gic cpu and distributor interfaces */
90 gicv2_driver_init(&plat_gicv2_gic_data);
91 gicv2_distif_init();
92 gicv2_pcpu_distif_init();
93 gicv2_cpuif_enable();
94 }
95
96 const mmap_region_t plat_agilex_mmap[] = {
97 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
98 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS),
99 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
100 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
101 MT_NON_CACHEABLE | MT_RW | MT_SECURE),
102 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
103 MT_DEVICE | MT_RW | MT_SECURE),
104 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS),
105 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS),
106 {0}
107 };
108
109 /*******************************************************************************
110 * Perform the very early platform specific architectural setup here. At the
111 * moment this is only intializes the mmu in a quick and dirty way.
112 ******************************************************************************/
bl31_plat_arch_setup(void)113 void bl31_plat_arch_setup(void)
114 {
115 const mmap_region_t bl_regions[] = {
116 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
117 MT_MEMORY | MT_RW | MT_SECURE),
118 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
119 MT_CODE | MT_SECURE),
120 MAP_REGION_FLAT(BL_RO_DATA_BASE,
121 BL_RO_DATA_END - BL_RO_DATA_BASE,
122 MT_RO_DATA | MT_SECURE),
123 #if USE_COHERENT_MEM
124 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
125 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
126 MT_DEVICE | MT_RW | MT_SECURE),
127 #endif
128 {0}
129 };
130
131 setup_page_tables(bl_regions, plat_agilex_mmap);
132 enable_mmu_el3(0);
133 }
134
135