1 /*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2019, Intel Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <arch.h>
9 #include <arch_helpers.h>
10 #include <assert.h>
11 #include <common/bl_common.h>
12 #include <drivers/arm/gicv2.h>
13 #include <drivers/ti/uart/uart_16550.h>
14 #include <lib/xlat_tables/xlat_tables.h>
15 #include <lib/mmio.h>
16 #include <plat/common/platform.h>
17 #include <platform_def.h>
18
19 #include "socfpga_private.h"
20 #include "socfpga_reset_manager.h"
21 #include "socfpga_system_manager.h"
22 #include "s10_memory_controller.h"
23 #include "s10_pinmux.h"
24 #include "s10_clock_manager.h"
25
26
27 static entry_point_info_t bl32_image_ep_info;
28 static entry_point_info_t bl33_image_ep_info;
29
bl31_plat_get_next_image_ep_info(uint32_t type)30 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
31 {
32 entry_point_info_t *next_image_info;
33
34 next_image_info = (type == NON_SECURE) ?
35 &bl33_image_ep_info : &bl32_image_ep_info;
36
37 /* None of the images on this platform can have 0x0 as the entrypoint */
38 if (next_image_info->pc)
39 return next_image_info;
40 else
41 return NULL;
42 }
43
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)44 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
45 u_register_t arg2, u_register_t arg3)
46 {
47 static console_16550_t console;
48
49 console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
50 &console);
51 /*
52 * Check params passed from BL31 should not be NULL,
53 */
54 void *from_bl2 = (void *) arg0;
55
56 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
57 assert(params_from_bl2 != NULL);
58
59 /*
60 * Copy BL32 (if populated by BL31) and BL33 entry point information.
61 * They are stored in Secure RAM, in BL31's address space.
62 */
63
64 if (params_from_bl2->h.type == PARAM_BL_PARAMS &&
65 params_from_bl2->h.version >= VERSION_2) {
66
67 bl_params_node_t *bl_params = params_from_bl2->head;
68
69 while (bl_params) {
70 if (bl_params->image_id == BL33_IMAGE_ID)
71 bl33_image_ep_info = *bl_params->ep_info;
72
73 bl_params = bl_params->next_params_info;
74 }
75 } else {
76 struct socfpga_bl31_params *arg_from_bl2 =
77 (struct socfpga_bl31_params *) from_bl2;
78
79 assert(arg_from_bl2->h.type == PARAM_BL31);
80 assert(arg_from_bl2->h.version >= VERSION_1);
81
82 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
83 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
84 }
85 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
86 }
87
88 static const interrupt_prop_t s10_interrupt_props[] = {
89 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
90 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
91 };
92
93 static unsigned int target_mask_array[PLATFORM_CORE_COUNT];
94
95 static const gicv2_driver_data_t plat_gicv2_gic_data = {
96 .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE,
97 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE,
98 .interrupt_props = s10_interrupt_props,
99 .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props),
100 .target_masks = target_mask_array,
101 .target_masks_num = ARRAY_SIZE(target_mask_array),
102 };
103
104 /*******************************************************************************
105 * Perform any BL3-1 platform setup code
106 ******************************************************************************/
bl31_platform_setup(void)107 void bl31_platform_setup(void)
108 {
109 /* Initialize the gic cpu and distributor interfaces */
110 gicv2_driver_init(&plat_gicv2_gic_data);
111 gicv2_distif_init();
112 gicv2_pcpu_distif_init();
113 gicv2_cpuif_enable();
114
115 /* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */
116 mmio_write_64(PLAT_CPU_RELEASE_ADDR,
117 (uint64_t)plat_secondary_cpus_bl31_entry);
118 }
119
120 const mmap_region_t plat_stratix10_mmap[] = {
121 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
122 MT_MEMORY | MT_RW | MT_NS),
123 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
124 MT_DEVICE | MT_RW | MT_NS),
125 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
126 MT_DEVICE | MT_RW | MT_SECURE),
127 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
128 MT_NON_CACHEABLE | MT_RW | MT_SECURE),
129 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
130 MT_DEVICE | MT_RW | MT_SECURE),
131 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
132 MT_DEVICE | MT_RW | MT_NS),
133 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
134 MT_DEVICE | MT_RW | MT_NS),
135 {0}
136 };
137
138 /*******************************************************************************
139 * Perform the very early platform specific architectural setup here. At the
140 * moment this is only intializes the mmu in a quick and dirty way.
141 ******************************************************************************/
bl31_plat_arch_setup(void)142 void bl31_plat_arch_setup(void)
143 {
144 const mmap_region_t bl_regions[] = {
145 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
146 MT_MEMORY | MT_RW | MT_SECURE),
147 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
148 MT_CODE | MT_SECURE),
149 MAP_REGION_FLAT(BL_RO_DATA_BASE,
150 BL_RO_DATA_END - BL_RO_DATA_BASE,
151 MT_RO_DATA | MT_SECURE),
152 #if USE_COHERENT_MEM
153 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
154 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
155 MT_DEVICE | MT_RW | MT_SECURE),
156 #endif
157 {0}
158 };
159
160 setup_page_tables(bl_regions, plat_stratix10_mmap);
161 enable_mmu_el3(0);
162 }
163
164