1 /*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8 #include <armada_common.h>
9
10 /*
11 * If bootrom is currently at BLE there's no need to include the memory
12 * maps structure at this point
13 */
14 #include <mvebu_def.h>
15 #ifndef IMAGE_BLE
16
17 /*****************************************************************************
18 * AMB Configuration
19 *****************************************************************************
20 */
21 struct addr_map_win amb_memory_map[] = {
22 /* CP1 SPI1 CS0 Direct Mode access */
23 {0xf900, 0x1000000, AMB_SPI1_CS0_ID},
24 };
25
marvell_get_amb_memory_map(struct addr_map_win ** win,uint32_t * size,uintptr_t base)26 int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size,
27 uintptr_t base)
28 {
29 *win = amb_memory_map;
30 if (*win == NULL)
31 *size = 0;
32 else
33 *size = ARRAY_SIZE(amb_memory_map);
34
35 return 0;
36 }
37 #endif
38
39 /*****************************************************************************
40 * IO WIN Configuration
41 *****************************************************************************
42 */
43 struct addr_map_win io_win_memory_map[] = {
44 /* CP1 (MCI0) internal regs */
45 {0x00000000f4000000, 0x2000000, MCI_0_TID},
46 #ifndef IMAGE_BLE
47 /* PCIe0 and SPI1_CS0 (RUNIT) on CP1*/
48 {0x00000000f9000000, 0x2000000, MCI_0_TID},
49 /* PCIe1 on CP1*/
50 {0x00000000fb000000, 0x1000000, MCI_0_TID},
51 /* PCIe2 on CP1*/
52 {0x00000000fc000000, 0x1000000, MCI_0_TID},
53 /* MCI 0 indirect window */
54 {MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID},
55 /* MCI 1 indirect window */
56 {MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID},
57 #endif
58 };
59
marvell_get_io_win_gcr_target(int ap_index)60 uint32_t marvell_get_io_win_gcr_target(int ap_index)
61 {
62 return PIDI_TID;
63 }
64
marvell_get_io_win_memory_map(int ap_index,struct addr_map_win ** win,uint32_t * size)65 int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win,
66 uint32_t *size)
67 {
68 *win = io_win_memory_map;
69 if (*win == NULL)
70 *size = 0;
71 else
72 *size = ARRAY_SIZE(io_win_memory_map);
73
74 return 0;
75 }
76
77 #ifndef IMAGE_BLE
78 /*****************************************************************************
79 * IOB Configuration
80 *****************************************************************************
81 */
82 struct addr_map_win iob_memory_map_cp0[] = {
83 /* CP0 */
84 /* PEX1_X1 window */
85 {0x00000000f7000000, 0x1000000, PEX1_TID},
86 /* PEX2_X1 window */
87 {0x00000000f8000000, 0x1000000, PEX2_TID},
88 /* PEX0_X4 window */
89 {0x00000000f6000000, 0x1000000, PEX0_TID},
90 {0x00000000c0000000, 0x30000000, PEX0_TID},
91 {0x0000000800000000, 0x100000000, PEX0_TID},
92 };
93
94 struct addr_map_win iob_memory_map_cp1[] = {
95 /* CP1 */
96 /* SPI1_CS0 (RUNIT) window */
97 {0x00000000f9000000, 0x1000000, RUNIT_TID},
98 /* PEX1_X1 window */
99 {0x00000000fb000000, 0x1000000, PEX1_TID},
100 /* PEX2_X1 window */
101 {0x00000000fc000000, 0x1000000, PEX2_TID},
102 /* PEX0_X4 window */
103 {0x00000000fa000000, 0x1000000, PEX0_TID}
104 };
105
marvell_get_iob_memory_map(struct addr_map_win ** win,uint32_t * size,uintptr_t base)106 int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size,
107 uintptr_t base)
108 {
109 switch (base) {
110 case MVEBU_CP_REGS_BASE(0):
111 *win = iob_memory_map_cp0;
112 *size = ARRAY_SIZE(iob_memory_map_cp0);
113 return 0;
114 case MVEBU_CP_REGS_BASE(1):
115 *win = iob_memory_map_cp1;
116 *size = ARRAY_SIZE(iob_memory_map_cp1);
117 return 0;
118 default:
119 *size = 0;
120 *win = 0;
121 return 1;
122 }
123 }
124 #endif
125
126 /*****************************************************************************
127 * CCU Configuration
128 *****************************************************************************
129 */
130 struct addr_map_win ccu_memory_map[] = {
131 #ifdef IMAGE_BLE
132 {0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */
133 #else
134 {0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */
135 {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
136 {0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */
137 #endif
138 };
139
marvell_get_ccu_gcr_target(int ap)140 uint32_t marvell_get_ccu_gcr_target(int ap)
141 {
142 return DRAM_0_TID;
143 }
144
marvell_get_ccu_memory_map(int ap,struct addr_map_win ** win,uint32_t * size)145 int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win,
146 uint32_t *size)
147 {
148 *win = ccu_memory_map;
149 *size = ARRAY_SIZE(ccu_memory_map);
150
151 return 0;
152 }
153
154 #ifndef IMAGE_BLE
155 /*****************************************************************************
156 * SoC PM configuration
157 *****************************************************************************
158 */
159 /* CP GPIO should be used and the GPIOs should be within same GPIO register */
160 struct power_off_method pm_cfg = {
161 .type = PMIC_GPIO,
162 .cfg.gpio.pin_count = 1,
163 .cfg.gpio.info = {{0, 35} },
164 .cfg.gpio.step_count = 7,
165 .cfg.gpio.seq = {1, 0, 1, 0, 1, 0, 1},
166 .cfg.gpio.delay_ms = 10,
167 };
168
plat_marvell_get_pm_cfg(void)169 void *plat_marvell_get_pm_cfg(void)
170 {
171 /* Return the PM configurations */
172 return &pm_cfg;
173 }
174
175 /* In reference to #ifndef IMAGE_BLE, this part is used for BLE only. */
176 #else
177 /*****************************************************************************
178 * SKIP IMAGE Configuration
179 *****************************************************************************
180 */
181 #if PLAT_RECOVERY_IMAGE_ENABLE
182 struct skip_image skip_im = {
183 .detection_method = GPIO,
184 .info.gpio.num = 33,
185 .info.gpio.button_state = HIGH,
186 .info.test.cp_ap = CP,
187 .info.test.cp_index = 0,
188 };
189
plat_marvell_get_skip_image_data(void)190 void *plat_marvell_get_skip_image_data(void)
191 {
192 /* Return the skip_image configurations */
193 return &skip_im;
194 }
195 #endif
196 #endif
197