1 /*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8 #include <arch_helpers.h>
9 #include <common/debug.h>
10 #include <drivers/mentor/mi2cv.h>
11 #include <lib/mmio.h>
12
13 #include <mv_ddr_if.h>
14 #include <mvebu_def.h>
15 #include <plat_marvell.h>
16
17 #define MVEBU_CP_MPP_CTRL37_OFFS 20
18 #define MVEBU_CP_MPP_CTRL38_OFFS 24
19 #define MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA 0x2
20 #define MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA 0x2
21
22 #define MVEBU_MPP_CTRL_MASK 0xf
23
24 /*
25 * This struct provides the DRAM training code with
26 * the appropriate board DRAM configuration
27 */
28 static struct mv_ddr_topology_map board_topology_map = {
29 /* Board with 1CS 8Gb x4 devices of Micron 2400T */
30 DEBUG_LEVEL_ERROR,
31 0x1, /* active interfaces */
32 /* cs_mask, mirror, dqs_swap, ck_swap X subphys */
33 { { { {0x1, 0x0, 0, 0}, /* FIXME: change the cs mask for all 64 bit */
34 {0x1, 0x0, 0, 0},
35 {0x1, 0x0, 0, 0},
36 {0x1, 0x0, 0, 0},
37 {0x1, 0x0, 0, 0},
38 {0x1, 0x0, 0, 0},
39 {0x1, 0x0, 0, 0},
40 {0x1, 0x0, 0, 0},
41 {0x1, 0x0, 0, 0} },
42 /* TODO: double check if the speed bin is 2400T */
43 SPEED_BIN_DDR_2400T, /* speed_bin */
44 MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */
45 MV_DDR_DIE_CAP_8GBIT, /* die capacity */
46 MV_DDR_FREQ_SAR, /* frequency */
47 0, 0, /* cas_l, cas_wl */
48 MV_DDR_TEMP_LOW} }, /* temperature */
49 MV_DDR_64BIT_BUS_MASK, /* subphys mask */
50 MV_DDR_CFG_SPD, /* ddr configuration data source */
51 { {0} }, /* raw spd data */
52 {0}, /* timing parameters */
53 { /* electrical configuration */
54 { /* memory electrical configuration */
55 MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
56 {
57 MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */
58 MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */
59 },
60 {
61 MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */
62 MV_DDR_RTT_WR_RZQ_DIV2 /* rtt_wr 2cs */
63 },
64 MV_DDR_DIC_RZQ_DIV7 /* dic */
65 },
66 { /* phy electrical configuration */
67 MV_DDR_OHM_30, /* data_drv_p */
68 MV_DDR_OHM_30, /* data_drv_n */
69 MV_DDR_OHM_30, /* ctrl_drv_p */
70 MV_DDR_OHM_30, /* ctrl_drv_n */
71 {
72 MV_DDR_OHM_60, /* odt_p 1cs */
73 MV_DDR_OHM_120 /* odt_p 2cs */
74 },
75 {
76 MV_DDR_OHM_60, /* odt_n 1cs */
77 MV_DDR_OHM_120 /* odt_n 2cs */
78 },
79 },
80 { /* mac electrical configuration */
81 MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
82 MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
83 MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
84 },
85 }
86 };
87
mv_ddr_topology_map_get(void)88 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
89 {
90 /* Return the board topology as defined in the board code */
91 return &board_topology_map;
92 }
93
mpp_config(void)94 static void mpp_config(void)
95 {
96 uint32_t val;
97 uintptr_t reg = MVEBU_CP_MPP_REGS(0, 4);
98
99 /* configure CP0 MPP 37 and 38 to i2c */
100 val = mmio_read_32(reg);
101 val &= ~((MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL37_OFFS) |
102 (MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL38_OFFS));
103 val |= (MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA << MVEBU_CP_MPP_CTRL37_OFFS) |
104 (MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA << MVEBU_CP_MPP_CTRL38_OFFS);
105 mmio_write_32(reg, val);
106 }
107
108 /*
109 * This function may modify the default DRAM parameters
110 * based on information received from SPD or bootloader
111 * configuration located on non volatile storage
112 */
plat_marvell_dram_update_topology(void)113 void plat_marvell_dram_update_topology(void)
114 {
115 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
116
117 INFO("Gathering DRAM information\n");
118
119 if (tm->cfg_src == MV_DDR_CFG_SPD) {
120 /* configure MPPs to enable i2c */
121 mpp_config();
122 /* initialize the i2c */
123 i2c_init((void *)MVEBU_CP0_I2C_BASE);
124 /* select SPD memory page 0 to access DRAM configuration */
125 i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 1);
126 /* read data from spd */
127 i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes,
128 sizeof(tm->spd_data.all_bytes));
129 }
130 }
131