1 /*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8 #include <common/debug.h>
9 #include <drivers/marvell/ap807_clocks_init.h>
10 #include <drivers/marvell/aro.h>
11 #include <drivers/marvell/ccu.h>
12 #include <drivers/marvell/io_win.h>
13 #include <drivers/marvell/mochi/ap_setup.h>
14 #include <drivers/marvell/mochi/cp110_setup.h>
15
16 #include <armada_common.h>
17 #include <mv_ddr_if.h>
18 #include <mvebu_def.h>
19 #include <plat_marvell.h>
20
21 /* Register for skip image use */
22 #define SCRATCH_PAD_REG2 0xF06F00A8
23 #define SCRATCH_PAD_SKIP_VAL 0x01
24 #define NUM_OF_GPIO_PER_REG 32
25
26 #define MMAP_SAVE_AND_CONFIG 0
27 #define MMAP_RESTORE_SAVED 1
28
29 /* SAR clock settings */
30 #define MVEBU_AP_GEN_MGMT_BASE (MVEBU_RFU_BASE + 0x8000)
31 #define MVEBU_AP_SAR_REG_BASE(r) (MVEBU_AP_GEN_MGMT_BASE + 0x200 +\
32 ((r) << 2))
33
34 #define SAR_CLOCK_FREQ_MODE_OFFSET (0)
35 #define SAR_CLOCK_FREQ_MODE_MASK (0x1f << SAR_CLOCK_FREQ_MODE_OFFSET)
36 #define SAR_PIDI_LOW_SPEED_OFFSET (20)
37 #define SAR_PIDI_LOW_SPEED_MASK (1 << SAR_PIDI_LOW_SPEED_OFFSET)
38 #define SAR_PIDI_LOW_SPEED_SHIFT (15)
39 #define SAR_PIDI_LOW_SPEED_SET (1 << SAR_PIDI_LOW_SPEED_SHIFT)
40
41 #define FREQ_MODE_AP_SAR_REG_NUM (0)
42 #define SAR_CLOCK_FREQ_MODE(v) (((v) & SAR_CLOCK_FREQ_MODE_MASK) >> \
43 SAR_CLOCK_FREQ_MODE_OFFSET)
44
45 #define AVS_I2C_EEPROM_ADDR 0x57 /* EEPROM */
46 #define AVS_EN_CTRL_REG (MVEBU_AP_GEN_MGMT_BASE + 0x130)
47 #define AVS_ENABLE_OFFSET (0)
48 #define AVS_SOFT_RESET_OFFSET (2)
49 #define AVS_TARGET_DELTA_OFFSET (21)
50
51 #ifndef MVEBU_SOC_AP807
52 /* AP806 SVC bits */
53 #define AVS_LOW_VDD_LIMIT_OFFSET (4)
54 #define AVS_HIGH_VDD_LIMIT_OFFSET (12)
55 #define AVS_VDD_LOW_LIMIT_MASK (0xFF << AVS_LOW_VDD_LIMIT_OFFSET)
56 #define AVS_VDD_HIGH_LIMIT_MASK (0xFF << AVS_HIGH_VDD_LIMIT_OFFSET)
57 #else
58 /* AP807 SVC bits */
59 #define AVS_LOW_VDD_LIMIT_OFFSET (3)
60 #define AVS_HIGH_VDD_LIMIT_OFFSET (13)
61 #define AVS_VDD_LOW_LIMIT_MASK (0x3FF << AVS_LOW_VDD_LIMIT_OFFSET)
62 #define AVS_VDD_HIGH_LIMIT_MASK (0x3FF << AVS_HIGH_VDD_LIMIT_OFFSET)
63 #endif
64
65 /* VDD limit is 0.9V for A70x0 @ CPU frequency < 1600MHz */
66 #define AVS_A7K_LOW_CLK_VALUE ((0x80 << AVS_TARGET_DELTA_OFFSET) | \
67 (0x1A << AVS_HIGH_VDD_LIMIT_OFFSET) | \
68 (0x1A << AVS_LOW_VDD_LIMIT_OFFSET) | \
69 (0x1 << AVS_SOFT_RESET_OFFSET) | \
70 (0x1 << AVS_ENABLE_OFFSET))
71 /* VDD limit is 1.0V for all A80x0 devices */
72 #define AVS_A8K_CLK_VALUE ((0x80 << AVS_TARGET_DELTA_OFFSET) | \
73 (0x24 << AVS_HIGH_VDD_LIMIT_OFFSET) | \
74 (0x24 << AVS_LOW_VDD_LIMIT_OFFSET) | \
75 (0x1 << AVS_SOFT_RESET_OFFSET) | \
76 (0x1 << AVS_ENABLE_OFFSET))
77 /* VDD limit is 0.82V for all A3900 devices
78 * AVS offsets are not the same as in A70x0
79 */
80 #define AVS_A3900_CLK_VALUE ((0x80u << 24) | \
81 (0x2c2 << 13) | \
82 (0x2c2 << 3) | \
83 (0x1 << AVS_SOFT_RESET_OFFSET) | \
84 (0x1 << AVS_ENABLE_OFFSET))
85 /* VDD is 0.88V for 2GHz clock */
86 #define AVS_A3900_HIGH_CLK_VALUE ((0x80u << 24) | \
87 (0x2f5 << 13) | \
88 (0x2f5 << 3) | \
89 (0x1 << AVS_SOFT_RESET_OFFSET) | \
90 (0x1 << AVS_ENABLE_OFFSET))
91
92 #define MVEBU_AP_EFUSE_SRV_CTRL_REG (MVEBU_AP_GEN_MGMT_BASE + 0x8)
93 #define EFUSE_SRV_CTRL_LD_SELECT_OFFS 6
94 #define EFUSE_SRV_CTRL_LD_SEL_USER_MASK (1 << EFUSE_SRV_CTRL_LD_SELECT_OFFS)
95
96
97 /*
98 * - Identification information in the LD-0 eFuse:
99 * DRO: LD0[74:65] - Not used by the SW
100 * Revision: LD0[78:75] - Not used by the SW
101 * Bin: LD0[80:79] - Not used by the SW
102 * SW Revision: LD0[115:113]
103 * Cluster 1 PWR: LD0[193] - if set to 1, power down CPU Cluster-1
104 * resulting in 2 CPUs active only (7020)
105 */
106 #define MVEBU_AP_LD_EFUSE_BASE (MVEBU_AP_GEN_MGMT_BASE + 0xF00)
107 /* Bits [94:63] - 32 data bits total */
108 #define MVEBU_AP_LD0_94_63_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x8)
109 /* Bits [125:95] - 31 data bits total, 32nd bit is parity for bits [125:63] */
110 #define MVEBU_AP_LD0_125_95_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0xC)
111 /* Bits [220:189] - 32 data bits total */
112 #define MVEBU_AP_LD0_220_189_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x18)
113 /* Offsets for the above 2 fields combined into single 64-bit value [125:63] */
114 #define EFUSE_AP_LD0_DRO_OFFS 2 /* LD0[74:65] */
115 #define EFUSE_AP_LD0_DRO_MASK 0x3FF
116 #define EFUSE_AP_LD0_REVID_OFFS 12 /* LD0[78:75] */
117 #define EFUSE_AP_LD0_REVID_MASK 0xF
118 #define EFUSE_AP_LD0_BIN_OFFS 16 /* LD0[80:79] */
119 #define EFUSE_AP_LD0_BIN_MASK 0x3
120 #define EFUSE_AP_LD0_SWREV_OFFS 50 /* LD0[115:113] */
121 #define EFUSE_AP_LD0_SWREV_MASK 0x7
122
123 #ifndef MVEBU_SOC_AP807
124 /* AP806 AVS work points in the LD0 eFuse
125 * SVC1 work point: LD0[88:81]
126 * SVC2 work point: LD0[96:89]
127 * SVC3 work point: LD0[104:97]
128 * SVC4 work point: LD0[112:105]
129 */
130 #define EFUSE_AP_LD0_SVC1_OFFS 18 /* LD0[88:81] */
131 #define EFUSE_AP_LD0_SVC2_OFFS 26 /* LD0[96:89] */
132 #define EFUSE_AP_LD0_SVC3_OFFS 34 /* LD0[104:97] */
133 #define EFUSE_AP_LD0_WP_MASK 0xFF
134 #else
135 /* AP807 AVS work points in the LD0 eFuse
136 * SVC1 work point: LD0[91:81]
137 * SVC2 work point: LD0[102:92]
138 * SVC3 work point: LD0[113:103]
139 */
140 #define EFUSE_AP_LD0_SVC1_OFFS 17 /* LD0[91:81] */
141 #define EFUSE_AP_LD0_SVC2_OFFS 28 /* LD0[102:92] */
142 #define EFUSE_AP_LD0_SVC3_OFFS 39 /* LD0[113:103] */
143 #define EFUSE_AP_LD0_WP_MASK 0x3FF
144 #endif
145
146 #define EFUSE_AP_LD0_SVC4_OFFS 42 /* LD0[112:105] */
147
148 #define EFUSE_AP_LD0_CLUSTER_DOWN_OFFS 4
149
150 #if MARVELL_SVC_TEST
151 #define MVEBU_CP_MPP_CTRL37_OFFS 20
152 #define MVEBU_CP_MPP_CTRL38_OFFS 24
153 #define MVEBU_CP_MPP_I2C_FUNC 2
154 #define MVEBU_MPP_CTRL_MASK 0xf
155 #endif
156
157 /* Return the AP revision of the chip */
ble_get_ap_type(void)158 static unsigned int ble_get_ap_type(void)
159 {
160 unsigned int chip_rev_id;
161
162 chip_rev_id = mmio_read_32(MVEBU_CSS_GWD_CTRL_IIDR2_REG);
163 chip_rev_id = ((chip_rev_id & GWD_IIDR2_CHIP_ID_MASK) >>
164 GWD_IIDR2_CHIP_ID_OFFSET);
165
166 return chip_rev_id;
167 }
168
169 /******************************************************************************
170 * The routine allows to save the CCU and IO windows configuration during DRAM
171 * setup and restore them afterwards before exiting the BLE stage.
172 * Such window configuration is required since not all default settings coming
173 * from the HW and the BootROM allow access to peripherals connected to
174 * all available CPn components.
175 * For instance, when the boot device is located on CP0, the IO window to CP1
176 * is not opened automatically by the HW and if the DRAM SPD is located on CP1
177 * i2c channel, it cannot be read at BLE stage.
178 * Therefore the DRAM init procedure have to provide access to all available
179 * CPn peripherals during the BLE stage by setting the CCU IO window to all
180 * CPnph addresses and by enabling the IO windows accordingly.
181 * Additionally this function configures the CCU GCR to DRAM, which allows
182 * usage or more than 4GB DRAM as it configured by the default CCU DRAM window.
183 *
184 * IN:
185 * MMAP_SAVE_AND_CONFIG - save the existing configuration and update it
186 * MMAP_RESTORE_SAVED - restore saved configuration
187 * OUT:
188 * NONE
189 ****************************************************************************
190 */
ble_plat_mmap_config(int restore)191 static void ble_plat_mmap_config(int restore)
192 {
193 if (restore == MMAP_RESTORE_SAVED) {
194 /* Restore all orig. settings that were modified by BLE stage */
195 ccu_restore_win_all(MVEBU_AP0);
196 /* Restore CCU */
197 iow_restore_win_all(MVEBU_AP0);
198 return;
199 }
200
201 /* Store original values */
202 ccu_save_win_all(MVEBU_AP0);
203 /* Save CCU */
204 iow_save_win_all(MVEBU_AP0);
205
206 init_ccu(MVEBU_AP0);
207 /* The configuration saved, now all the changes can be done */
208 init_io_win(MVEBU_AP0);
209 }
210
211 /****************************************************************************
212 * Setup Adaptive Voltage Switching - this is required for some platforms
213 ****************************************************************************
214 */
215 #if !MARVELL_SVC_TEST
ble_plat_avs_config(void)216 static void ble_plat_avs_config(void)
217 {
218 uint32_t freq_mode, device_id;
219 uint32_t avs_val = 0;
220
221 freq_mode =
222 SAR_CLOCK_FREQ_MODE(mmio_read_32(MVEBU_AP_SAR_REG_BASE(
223 FREQ_MODE_AP_SAR_REG_NUM)));
224 /* Check which SoC is running and act accordingly */
225 if (ble_get_ap_type() == CHIP_ID_AP807) {
226 /* Increase CPU voltage for higher CPU clock */
227 if (freq_mode == CPU_2000_DDR_1200_RCLK_1200)
228 avs_val = AVS_A3900_HIGH_CLK_VALUE;
229 else
230 avs_val = AVS_A3900_CLK_VALUE;
231 } else {
232 /* Check which SoC is running and act accordingly */
233 device_id = cp110_device_id_get(MVEBU_CP_REGS_BASE(0));
234 switch (device_id) {
235 case MVEBU_80X0_DEV_ID:
236 case MVEBU_80X0_CP115_DEV_ID:
237 /* Always fix the default AVS value on A80x0 */
238 avs_val = AVS_A8K_CLK_VALUE;
239 break;
240 case MVEBU_70X0_DEV_ID:
241 case MVEBU_70X0_CP115_DEV_ID:
242 /* Fix AVS for CPU clocks lower than 1600MHz on A70x0 */
243 if ((freq_mode > CPU_1600_DDR_900_RCLK_900_2) &&
244 (freq_mode < CPU_DDR_RCLK_INVALID))
245 avs_val = AVS_A7K_LOW_CLK_VALUE;
246 break;
247 default:
248 ERROR("Unsupported Device ID 0x%x\n", device_id);
249 return;
250 }
251 }
252
253 if (avs_val) {
254 VERBOSE("AVS: Setting AVS CTRL to 0x%x\n", avs_val);
255 mmio_write_32(AVS_EN_CTRL_REG, avs_val);
256 }
257 }
258 #endif
259 /******************************************************************************
260 * Update or override current AVS work point value using data stored in EEPROM
261 * This is only required by QA/validation flows and activated by
262 * MARVELL_SVC_TEST flag.
263 *
264 * The function is expected to be called twice.
265 *
266 * First time with AVS value of 0 for testing if the EEPROM requests completely
267 * override the AVS value and bypass the eFuse test
268 *
269 * Second time - with non-zero AVS value obtained from eFuses as an input.
270 * In this case the EEPROM may contain AVS correction value (either positive
271 * or negative) that is added to the input AVS value and returned back for
272 * further processing.
273 ******************************************************************************
274 */
avs_update_from_eeprom(uint32_t avs_workpoint)275 static uint32_t avs_update_from_eeprom(uint32_t avs_workpoint)
276 {
277 uint32_t new_wp = avs_workpoint;
278 #if MARVELL_SVC_TEST
279 /* ---------------------------------------------------------------------
280 * EEPROM | Data description (avs_step)
281 * address |
282 * ---------------------------------------------------------------------
283 * 0x120 | AVS workpoint correction value
284 * | if not 0 and not 0xff, correct the AVS taken from eFuse
285 * | by the number of steps indicated by bit[6:0]
286 * | bit[7] defines correction direction.
287 * | If bit[7]=1, add the value from bit[6:0] to AVS workpoint,
288 * | othervise substruct this value from AVS workpoint.
289 * ---------------------------------------------------------------------
290 * 0x121 | AVS workpoint override value
291 * | Override the AVS workpoint with the value stored in this
292 * | byte. When running on AP806, the AVS workpoint is 7 bits
293 * | wide and override value is valid when bit[6:0] holds
294 * | value greater than zero and smaller than 0x33.
295 * | When running on AP807, the AVS workpoint is 10 bits wide.
296 * | Additional 2 MSB bits are supplied by EEPROM byte 0x122.
297 * | AVS override value is valid when byte @ 0x121 and bit[1:0]
298 * | of byte @ 0x122 combined have non-zero value.
299 * ---------------------------------------------------------------------
300 * 0x122 | Extended AVS workpoint override value
301 * | Valid only for AP807 platforms and must be less than 0x4
302 * ---------------------------------------------------------------------
303 */
304 static uint8_t avs_step[3] = {0};
305 uintptr_t reg;
306 uint32_t val;
307 unsigned int ap_type = ble_get_ap_type();
308
309 /* Always happens on second call to this function */
310 if (avs_workpoint != 0) {
311 /* Get correction steps from the EEPROM */
312 if ((avs_step[0] != 0) && (avs_step[0] != 0xff)) {
313 NOTICE("AVS request to step %s by 0x%x from old 0x%x\n",
314 avs_step[0] & 0x80 ? "DOWN" : "UP",
315 avs_step[0] & 0x7f, new_wp);
316 if (avs_step[0] & 0x80)
317 new_wp -= avs_step[0] & 0x7f;
318 else
319 new_wp += avs_step[0] & 0x7f;
320 }
321
322 return new_wp;
323 }
324
325 /* AVS values are located in EEPROM
326 * at CP0 i2c bus #0, device 0x57 offset 0x120
327 * The SDA and SCK pins of CP0 i2c-0: MPP[38:37], i2c function 0x2.
328 */
329 reg = MVEBU_CP_MPP_REGS(0, 4);
330 val = mmio_read_32(reg);
331 val &= ~((MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL37_OFFS) |
332 (MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL38_OFFS));
333 val |= (MVEBU_CP_MPP_I2C_FUNC << MVEBU_CP_MPP_CTRL37_OFFS) |
334 (MVEBU_CP_MPP_I2C_FUNC << MVEBU_CP_MPP_CTRL38_OFFS);
335 mmio_write_32(reg, val);
336
337 /* Init CP0 i2c-0 */
338 i2c_init((void *)(MVEBU_CP0_I2C_BASE));
339
340 /* Read EEPROM only once at the fist call! */
341 i2c_read(AVS_I2C_EEPROM_ADDR, 0x120, 2, avs_step, 3);
342 NOTICE("== SVC test build ==\n");
343 NOTICE("EEPROM holds values 0x%x, 0x%x and 0x%x\n",
344 avs_step[0], avs_step[1], avs_step[2]);
345
346 /* Override the AVS value? */
347 if ((ap_type != CHIP_ID_AP807) && (avs_step[1] < 0x33)) {
348 /* AP806 - AVS is 7 bits */
349 new_wp = avs_step[1];
350
351 } else if (ap_type == CHIP_ID_AP807 && (avs_step[2] < 0x4)) {
352 /* AP807 - AVS is 10 bits */
353 new_wp = avs_step[2];
354 new_wp <<= 8;
355 new_wp |= avs_step[1];
356 }
357
358 if (new_wp == 0)
359 NOTICE("Ignore BAD AVS Override value in EEPROM!\n");
360 else
361 NOTICE("Override AVS by EEPROM value 0x%x\n", new_wp);
362 #endif /* MARVELL_SVC_TEST */
363 return new_wp;
364 }
365
366 /****************************************************************************
367 * SVC flow - v0.10
368 * The feature is intended to configure AVS value according to eFuse values
369 * that are burned individually for each SoC during the test process.
370 * Primary AVS value is stored in HD efuse and processed on power on
371 * by the HW engine
372 * Secondary AVS value is located in LD efuse and contains 4 work points for
373 * various CPU frequencies.
374 * The Secondary AVS value is only taken into account if the SW Revision stored
375 * in the efuse is greater than 0 and the CPU is running in a certain speed.
376 ****************************************************************************
377 */
ble_plat_svc_config(void)378 static void ble_plat_svc_config(void)
379 {
380 uint32_t reg_val, avs_workpoint, freq_pidi_mode;
381 uint64_t efuse;
382 uint32_t device_id, single_cluster;
383 uint16_t svc[4], perr[4], i, sw_ver;
384 unsigned int ap_type;
385
386 /* Set access to LD0 */
387 avs_workpoint = avs_update_from_eeprom(0);
388 if (avs_workpoint)
389 goto set_aws_wp;
390
391 /* Set access to LD0 */
392 reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG);
393 reg_val &= ~EFUSE_SRV_CTRL_LD_SELECT_OFFS;
394 mmio_write_32(MVEBU_AP_EFUSE_SRV_CTRL_REG, reg_val);
395
396 /* Obtain the value of LD0[125:63] */
397 efuse = mmio_read_32(MVEBU_AP_LD0_125_95_EFUSE_OFFS);
398 efuse <<= 32;
399 efuse |= mmio_read_32(MVEBU_AP_LD0_94_63_EFUSE_OFFS);
400
401 /* SW Revision:
402 * Starting from SW revision 1 the SVC flow is supported.
403 * SW version 0 (efuse not programmed) should follow the
404 * regular AVS update flow.
405 */
406 sw_ver = (efuse >> EFUSE_AP_LD0_SWREV_OFFS) & EFUSE_AP_LD0_SWREV_MASK;
407 if (sw_ver < 1) {
408 NOTICE("SVC: SW Revision 0x%x. SVC is not supported\n", sw_ver);
409 #if MARVELL_SVC_TEST
410 NOTICE("SVC_TEST: AVS bypassed\n");
411
412 #else
413 ble_plat_avs_config();
414 #endif
415 return;
416 }
417
418 /* Frequency mode from SAR */
419 freq_pidi_mode = SAR_CLOCK_FREQ_MODE(
420 mmio_read_32(
421 MVEBU_AP_SAR_REG_BASE(
422 FREQ_MODE_AP_SAR_REG_NUM)));
423
424 /* Decode all SVC work points */
425 svc[0] = (efuse >> EFUSE_AP_LD0_SVC1_OFFS) & EFUSE_AP_LD0_WP_MASK;
426 svc[1] = (efuse >> EFUSE_AP_LD0_SVC2_OFFS) & EFUSE_AP_LD0_WP_MASK;
427 svc[2] = (efuse >> EFUSE_AP_LD0_SVC3_OFFS) & EFUSE_AP_LD0_WP_MASK;
428
429 /* Fetch AP type to distinguish between AP806 and AP807 */
430 ap_type = ble_get_ap_type();
431
432 if (ap_type != CHIP_ID_AP807) {
433 svc[3] = (efuse >> EFUSE_AP_LD0_SVC4_OFFS)
434 & EFUSE_AP_LD0_WP_MASK;
435 INFO("SVC: Efuse WP: [0]=0x%x, [1]=0x%x, [2]=0x%x, [3]=0x%x\n",
436 svc[0], svc[1], svc[2], svc[3]);
437 } else {
438 INFO("SVC: Efuse WP: [0]=0x%x, [1]=0x%x, [2]=0x%x\n",
439 svc[0], svc[1], svc[2]);
440 }
441
442 /* Validate parity of SVC workpoint values */
443 for (i = 0; i < 4; i++) {
444 uint8_t parity, bit;
445
446 perr[i] = 0;
447
448 for (bit = 1, parity = svc[i] & 1; bit < 7; bit++)
449 parity ^= (svc[i] >> bit) & 1;
450
451 /* Starting from SW version 2, the parity check is mandatory */
452 if ((sw_ver > 1) && (parity != ((svc[i] >> 7) & 1)))
453 perr[i] = 1; /* register the error */
454 }
455
456 single_cluster = mmio_read_32(MVEBU_AP_LD0_220_189_EFUSE_OFFS);
457 single_cluster = (single_cluster >> EFUSE_AP_LD0_CLUSTER_DOWN_OFFS) & 1;
458
459 device_id = cp110_device_id_get(MVEBU_CP_REGS_BASE(0));
460 if (device_id == MVEBU_80X0_DEV_ID ||
461 device_id == MVEBU_80X0_CP115_DEV_ID) {
462 /* A8040/A8020 */
463 NOTICE("SVC: DEV ID: %s, FREQ Mode: 0x%x\n",
464 single_cluster == 0 ? "8040" : "8020", freq_pidi_mode);
465 switch (freq_pidi_mode) {
466 case CPU_1800_DDR_1200_RCLK_1200:
467 case CPU_1800_DDR_1050_RCLK_1050:
468 if (perr[1])
469 goto perror;
470 avs_workpoint = svc[1];
471 break;
472 case CPU_1600_DDR_1050_RCLK_1050:
473 case CPU_1600_DDR_900_RCLK_900_2:
474 if (perr[2])
475 goto perror;
476 avs_workpoint = svc[2];
477 break;
478 case CPU_1300_DDR_800_RCLK_800:
479 case CPU_1300_DDR_650_RCLK_650:
480 if (perr[3])
481 goto perror;
482 avs_workpoint = svc[3];
483 break;
484 case CPU_2000_DDR_1200_RCLK_1200:
485 case CPU_2000_DDR_1050_RCLK_1050:
486 default:
487 if (perr[0])
488 goto perror;
489 avs_workpoint = svc[0];
490 break;
491 }
492 } else if (device_id == MVEBU_70X0_DEV_ID ||
493 device_id == MVEBU_70X0_CP115_DEV_ID) {
494 /* A7040/A7020/A6040 */
495 NOTICE("SVC: DEV ID: %s, FREQ Mode: 0x%x\n",
496 single_cluster == 0 ? "7040" : "7020", freq_pidi_mode);
497 switch (freq_pidi_mode) {
498 case CPU_1400_DDR_800_RCLK_800:
499 if (single_cluster) {/* 7020 */
500 if (perr[1])
501 goto perror;
502 avs_workpoint = svc[1];
503 } else {
504 if (perr[0])
505 goto perror;
506 avs_workpoint = svc[0];
507 }
508 break;
509 case CPU_1200_DDR_800_RCLK_800:
510 if (single_cluster) {/* 7020 */
511 if (perr[2])
512 goto perror;
513 avs_workpoint = svc[2];
514 } else {
515 if (perr[1])
516 goto perror;
517 avs_workpoint = svc[1];
518 }
519 break;
520 case CPU_800_DDR_800_RCLK_800:
521 case CPU_1000_DDR_800_RCLK_800:
522 if (single_cluster) {/* 7020 */
523 if (perr[3])
524 goto perror;
525 avs_workpoint = svc[3];
526 } else {
527 if (perr[2])
528 goto perror;
529 avs_workpoint = svc[2];
530 }
531 break;
532 case CPU_600_DDR_800_RCLK_800:
533 if (perr[3])
534 goto perror;
535 avs_workpoint = svc[3]; /* Same for 6040 and 7020 */
536 break;
537 case CPU_1600_DDR_800_RCLK_800: /* 7020 only */
538 default:
539 if (single_cluster) {/* 7020 */
540 if (perr[0])
541 goto perror;
542 avs_workpoint = svc[0];
543 } else
544 avs_workpoint = 0;
545 break;
546 }
547 } else if (device_id == MVEBU_3900_DEV_ID) {
548 NOTICE("SVC: DEV ID: %s, FREQ Mode: 0x%x\n",
549 "3900", freq_pidi_mode);
550 switch (freq_pidi_mode) {
551 case CPU_1600_DDR_1200_RCLK_1200:
552 if (perr[0])
553 goto perror;
554 avs_workpoint = svc[0];
555 break;
556 case CPU_1300_DDR_800_RCLK_800:
557 if (perr[1])
558 goto perror;
559 avs_workpoint = svc[1];
560 break;
561 default:
562 if (perr[0])
563 goto perror;
564 avs_workpoint = svc[0];
565 break;
566 }
567 } else {
568 ERROR("SVC: Unsupported Device ID 0x%x\n", device_id);
569 return;
570 }
571
572 /* Set AVS control if needed */
573 if (avs_workpoint == 0) {
574 ERROR("SVC: AVS work point not changed\n");
575 return;
576 }
577
578 /* Remove parity bit */
579 if (ap_type != CHIP_ID_AP807)
580 avs_workpoint &= 0x7F;
581
582 /* Update WP from EEPROM if needed */
583 avs_workpoint = avs_update_from_eeprom(avs_workpoint);
584
585 set_aws_wp:
586 reg_val = mmio_read_32(AVS_EN_CTRL_REG);
587 NOTICE("SVC: AVS work point changed from 0x%x to 0x%x\n",
588 (reg_val & AVS_VDD_LOW_LIMIT_MASK) >> AVS_LOW_VDD_LIMIT_OFFSET,
589 avs_workpoint);
590 reg_val &= ~(AVS_VDD_LOW_LIMIT_MASK | AVS_VDD_HIGH_LIMIT_MASK);
591 reg_val |= 0x1 << AVS_ENABLE_OFFSET;
592 reg_val |= avs_workpoint << AVS_HIGH_VDD_LIMIT_OFFSET;
593 reg_val |= avs_workpoint << AVS_LOW_VDD_LIMIT_OFFSET;
594 mmio_write_32(AVS_EN_CTRL_REG, reg_val);
595 return;
596
597 perror:
598 ERROR("Failed SVC WP[%d] parity check!\n", i);
599 ERROR("Ignoring the WP values\n");
600 }
601
602 #if PLAT_RECOVERY_IMAGE_ENABLE
ble_skip_image_i2c(struct skip_image * skip_im)603 static int ble_skip_image_i2c(struct skip_image *skip_im)
604 {
605 ERROR("skipping image using i2c is not supported\n");
606 /* not supported */
607 return 0;
608 }
609
ble_skip_image_other(struct skip_image * skip_im)610 static int ble_skip_image_other(struct skip_image *skip_im)
611 {
612 ERROR("implementation missing for skip image request\n");
613 /* not supported, make your own implementation */
614 return 0;
615 }
616
ble_skip_image_gpio(struct skip_image * skip_im)617 static int ble_skip_image_gpio(struct skip_image *skip_im)
618 {
619 unsigned int val;
620 unsigned int mpp_address = 0;
621 unsigned int offset = 0;
622
623 switch (skip_im->info.test.cp_ap) {
624 case(CP):
625 mpp_address = MVEBU_CP_GPIO_DATA_IN(skip_im->info.test.cp_index,
626 skip_im->info.gpio.num);
627 if (skip_im->info.gpio.num > NUM_OF_GPIO_PER_REG)
628 offset = skip_im->info.gpio.num - NUM_OF_GPIO_PER_REG;
629 else
630 offset = skip_im->info.gpio.num;
631 break;
632 case(AP):
633 mpp_address = MVEBU_AP_GPIO_DATA_IN;
634 offset = skip_im->info.gpio.num;
635 break;
636 }
637
638 val = mmio_read_32(mpp_address);
639 val &= (1 << offset);
640 if ((!val && skip_im->info.gpio.button_state == HIGH) ||
641 (val && skip_im->info.gpio.button_state == LOW)) {
642 mmio_write_32(SCRATCH_PAD_REG2, SCRATCH_PAD_SKIP_VAL);
643 return 1;
644 }
645
646 return 0;
647 }
648
649 /*
650 * This function checks if there's a skip image request:
651 * return values:
652 * 1: (true) images request been made.
653 * 0: (false) no image request been made.
654 */
ble_skip_current_image(void)655 static int ble_skip_current_image(void)
656 {
657 struct skip_image *skip_im;
658
659 /*fetching skip image info*/
660 skip_im = (struct skip_image *)plat_marvell_get_skip_image_data();
661
662 if (skip_im == NULL)
663 return 0;
664
665 /* check if skipping image request has already been made */
666 if (mmio_read_32(SCRATCH_PAD_REG2) == SCRATCH_PAD_SKIP_VAL)
667 return 0;
668
669 switch (skip_im->detection_method) {
670 case GPIO:
671 return ble_skip_image_gpio(skip_im);
672 case I2C:
673 return ble_skip_image_i2c(skip_im);
674 case USER_DEFINED:
675 return ble_skip_image_other(skip_im);
676 }
677
678 return 0;
679 }
680 #endif
681
682
ble_plat_setup(int * skip)683 int ble_plat_setup(int *skip)
684 {
685 int ret;
686 unsigned int freq_mode;
687
688 /* Power down unused CPUs */
689 plat_marvell_early_cpu_powerdown();
690
691 /*
692 * Save the current CCU configuration and make required changes:
693 * - Allow access to DRAM larger than 4GB
694 * - Open memory access to all CPn peripherals
695 */
696 ble_plat_mmap_config(MMAP_SAVE_AND_CONFIG);
697
698 #if PLAT_RECOVERY_IMAGE_ENABLE
699 /* Check if there's a skip request to bootRom recovery Image */
700 if (ble_skip_current_image()) {
701 /* close memory access to all CPn peripherals. */
702 ble_plat_mmap_config(MMAP_RESTORE_SAVED);
703 *skip = 1;
704 return 0;
705 }
706 #endif
707 /* Do required CP-110 setups for BLE stage */
708 cp110_ble_init(MVEBU_CP_REGS_BASE(0));
709
710 /* Setup AVS */
711 ble_plat_svc_config();
712
713 /* read clk option from sampled-at-reset register */
714 freq_mode =
715 SAR_CLOCK_FREQ_MODE(mmio_read_32(MVEBU_AP_SAR_REG_BASE(
716 FREQ_MODE_AP_SAR_REG_NUM)));
717
718 /* work with PLL clock driver in AP807 */
719 if (ble_get_ap_type() == CHIP_ID_AP807)
720 ap807_clocks_init(freq_mode);
721
722 /* Do required AP setups for BLE stage */
723 ap_ble_init();
724
725 /* Update DRAM topology (scan DIMM SPDs) */
726 plat_marvell_dram_update_topology();
727
728 /* Kick it in */
729 ret = dram_init();
730
731 /* Restore the original CCU configuration before exit from BLE */
732 ble_plat_mmap_config(MMAP_RESTORE_SAVED);
733
734 return ret;
735 }
736