1/* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8#include <asm_macros.S> 9#include <cortex_a72.h> 10#ifndef PLAT_a3700 11#include <drivers/marvell/ccu.h> 12#include <drivers/marvell/cache_llc.h> 13#endif 14#include <marvell_def.h> 15#include <platform_def.h> 16 17 .weak plat_marvell_calc_core_pos 18 .weak plat_my_core_pos 19 .globl plat_crash_console_init 20 .globl plat_crash_console_putc 21 .globl plat_crash_console_flush 22 .globl platform_mem_init 23 .globl disable_mmu_dcache 24 .globl invalidate_tlb_all 25 .globl platform_unmap_sram 26 .globl disable_sram 27 .globl disable_icache 28 .globl invalidate_icache_all 29 .globl marvell_exit_bootrom 30 .globl ca72_l2_enable_unique_clean 31 32 /* ----------------------------------------------------- 33 * unsigned int plat_my_core_pos(void) 34 * This function uses the plat_marvell_calc_core_pos() 35 * definition to get the index of the calling CPU. 36 * ----------------------------------------------------- 37 */ 38func plat_my_core_pos 39 mrs x0, mpidr_el1 40 b plat_marvell_calc_core_pos 41endfunc plat_my_core_pos 42 43 /* ----------------------------------------------------- 44 * unsigned int plat_marvell_calc_core_pos(uint64_t mpidr) 45 * Helper function to calculate the core position. 46 * With this function: CorePos = (ClusterId * 2) + 47 * CoreId 48 * ----------------------------------------------------- 49 */ 50func plat_marvell_calc_core_pos 51 and x1, x0, #MPIDR_CPU_MASK 52 and x0, x0, #MPIDR_CLUSTER_MASK 53 add x0, x1, x0, LSR #7 54 ret 55endfunc plat_marvell_calc_core_pos 56 57 /* --------------------------------------------- 58 * int plat_crash_console_init(void) 59 * Function to initialize the crash console 60 * without a C Runtime to print crash report. 61 * Clobber list : x0, x1, x2 62 * --------------------------------------------- 63 */ 64func plat_crash_console_init 65 mov_imm x0, PLAT_MARVELL_CRASH_UART_BASE 66 mov_imm x1, PLAT_MARVELL_CRASH_UART_CLK_IN_HZ 67 mov_imm x2, MARVELL_CONSOLE_BAUDRATE 68#ifdef PLAT_a3700 69 b console_a3700_core_init 70#else 71 b console_16550_core_init 72#endif 73endfunc plat_crash_console_init 74 75 /* --------------------------------------------- 76 * int plat_crash_console_putc(int c) 77 * Function to print a character on the crash 78 * console without a C Runtime. 79 * Clobber list : x1, x2 80 * --------------------------------------------- 81 */ 82func plat_crash_console_putc 83 mov_imm x1, PLAT_MARVELL_CRASH_UART_BASE 84#ifdef PLAT_a3700 85 86 b console_a3700_core_putc 87#else 88 b console_16550_core_putc 89#endif 90endfunc plat_crash_console_putc 91 92 /* --------------------------------------------- 93 * int plat_crash_console_flush() 94 * Function to force a write of all buffered 95 * data that hasn't been output. 96 * Out : return -1 on error else return 0. 97 * Clobber list : r0 98 * --------------------------------------------- 99 */ 100func plat_crash_console_flush 101 mov_imm x0, PLAT_MARVELL_CRASH_UART_BASE 102#ifdef PLAT_a3700 103 b console_a3700_core_flush 104#else 105 b console_16550_core_flush 106#endif 107endfunc plat_crash_console_flush 108 109 /* --------------------------------------------------------------------- 110 * We don't need to carry out any memory initialization on ARM 111 * platforms. The Secure RAM is accessible straight away. 112 * --------------------------------------------------------------------- 113 */ 114func platform_mem_init 115 ret 116endfunc platform_mem_init 117 118 /* ----------------------------------------------------- 119 * Disable icache, dcache, and MMU 120 * ----------------------------------------------------- 121 */ 122func disable_mmu_dcache 123 mrs x0, sctlr_el3 124 bic x0, x0, 0x1 /* M bit - MMU */ 125 bic x0, x0, 0x4 /* C bit - Dcache L1 & L2 */ 126 msr sctlr_el3, x0 127 isb 128 b mmu_off 129mmu_off: 130 ret 131endfunc disable_mmu_dcache 132 133 /* ----------------------------------------------------- 134 * Disable all TLB entries 135 * ----------------------------------------------------- 136 */ 137func invalidate_tlb_all 138 tlbi alle3 139 dsb sy 140 isb 141 ret 142endfunc invalidate_tlb_all 143 144 /* ----------------------------------------------------- 145 * Disable the i cache 146 * ----------------------------------------------------- 147 */ 148func disable_icache 149 mrs x0, sctlr_el3 150 bic x0, x0, 0x1000 /* I bit - Icache L1 & L2 */ 151 msr sctlr_el3, x0 152 isb 153 ret 154endfunc disable_icache 155 156 /* ----------------------------------------------------- 157 * Disable all of the i caches 158 * ----------------------------------------------------- 159 */ 160func invalidate_icache_all 161 ic ialluis 162 isb sy 163 ret 164endfunc invalidate_icache_all 165 166 /* ----------------------------------------------------- 167 * Clear the SRAM enabling bit to unmap SRAM 168 * ----------------------------------------------------- 169 */ 170func platform_unmap_sram 171 ldr x0, =CCU_SRAM_WIN_CR 172 str wzr, [x0] 173 ret 174endfunc platform_unmap_sram 175 176 /* ----------------------------------------------------- 177 * Disable the SRAM 178 * ----------------------------------------------------- 179 */ 180func disable_sram 181 /* Disable the line lockings. They must be disabled expictly 182 * or the OS will have problems using the cache */ 183 ldr x1, =MASTER_LLC_TC0_LOCK 184 str wzr, [x1] 185 186 /* Invalidate all ways */ 187 ldr w1, =LLC_WAY_MASK 188 ldr x0, =MASTER_L2X0_INV_WAY 189 str w1, [x0] 190 191 /* Finally disable LLC */ 192 ldr x0, =MASTER_LLC_CTRL 193 str wzr, [x0] 194 195 ret 196endfunc disable_sram 197 198 /* ----------------------------------------------------- 199 * Operation when exit bootROM: 200 * Disable the MMU 201 * Disable and invalidate the dcache 202 * Unmap and disable the SRAM 203 * Disable and invalidate the icache 204 * ----------------------------------------------------- 205 */ 206func marvell_exit_bootrom 207 /* Save the system restore address */ 208 mov x28, x0 209 210 /* Close the caches and MMU */ 211 bl disable_mmu_dcache 212 213 /* 214 * There is nothing important in the caches now, 215 * so invalidate them instead of cleaning. 216 */ 217 adr x0, __RW_START__ 218 adr x1, __RW_END__ 219 sub x1, x1, x0 220 bl inv_dcache_range 221 bl invalidate_tlb_all 222 223 /* 224 * Clean the memory mapping of SRAM 225 * the DDR mapping will remain to enable boot image to execute 226 */ 227 bl platform_unmap_sram 228 229 /* Disable the SRAM */ 230 bl disable_sram 231 232 /* Disable and invalidate icache */ 233 bl disable_icache 234 bl invalidate_icache_all 235 236 mov x0, x28 237 br x0 238endfunc marvell_exit_bootrom 239 240 /* 241 * Enable L2 UniqueClean evictions with data 242 */ 243func ca72_l2_enable_unique_clean 244 245 mrs x0, CORTEX_A72_L2ACTLR_EL1 246 orr x0, x0, #CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN 247 msr CORTEX_A72_L2ACTLR_EL1, x0 248 249 ret 250endfunc ca72_l2_enable_unique_clean 251