1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef FLOWCTRL_H 8 #define FLOWCTRL_H 9 10 #include <lib/mmio.h> 11 12 #include <tegra_def.h> 13 14 #define FLOWCTRL_HALT_CPU0_EVENTS (0x0U) 15 #define FLOWCTRL_WAITEVENT (2U << 29) 16 #define FLOWCTRL_WAIT_FOR_INTERRUPT (4U << 29) 17 #define FLOWCTRL_JTAG_RESUME (1U << 28) 18 #define FLOWCTRL_HALT_SCLK (1U << 27) 19 #define FLOWCTRL_HALT_LIC_IRQ (1U << 11) 20 #define FLOWCTRL_HALT_LIC_FIQ (1U << 10) 21 #define FLOWCTRL_HALT_GIC_IRQ (1U << 9) 22 #define FLOWCTRL_HALT_GIC_FIQ (1U << 8) 23 #define FLOWCTRL_HALT_BPMP_EVENTS (0x4U) 24 #define FLOWCTRL_CPU0_CSR (0x8U) 25 #define FLOWCTRL_CSR_HALT_MASK (1U << 22) 26 #define FLOWCTRL_CSR_PWR_OFF_STS (1U << 16) 27 #define FLOWCTRL_CSR_INTR_FLAG (1U << 15) 28 #define FLOWCTRL_CSR_EVENT_FLAG (1U << 14) 29 #define FLOWCTRL_CSR_IMMEDIATE_WAKE (1U << 3) 30 #define FLOWCTRL_CSR_ENABLE (1U << 0) 31 #define FLOWCTRL_HALT_CPU1_EVENTS (0x14U) 32 #define FLOWCTRL_CPU1_CSR (0x18U) 33 #define FLOW_CTLR_FLOW_DBG_QUAL (0x50U) 34 #define FLOWCTRL_FIQ2CCPLEX_ENABLE (1U << 28) 35 #define FLOWCTRL_FC_SEQ_INTERCEPT (0x5cU) 36 #define INTERCEPT_IRQ_PENDING (0xffU) 37 #define INTERCEPT_HVC (U(1) << 21) 38 #define INTERCEPT_ENTRY_CC4 (U(1) << 20) 39 #define INTERCEPT_ENTRY_PG_NONCPU (U(1) << 19) 40 #define INTERCEPT_EXIT_PG_NONCPU (U(1) << 18) 41 #define INTERCEPT_ENTRY_RG_CPU (U(1) << 17) 42 #define INTERCEPT_EXIT_RG_CPU (U(1) << 16) 43 #define INTERCEPT_ENTRY_PG_CORE0 (U(1) << 15) 44 #define INTERCEPT_EXIT_PG_CORE0 (U(1) << 14) 45 #define INTERCEPT_ENTRY_PG_CORE1 (U(1) << 13) 46 #define INTERCEPT_EXIT_PG_CORE1 (U(1) << 12) 47 #define INTERCEPT_ENTRY_PG_CORE2 (U(1) << 11) 48 #define INTERCEPT_EXIT_PG_CORE2 (U(1) << 10) 49 #define INTERCEPT_ENTRY_PG_CORE3 (U(1) << 9) 50 #define INTERCEPT_EXIT_PG_CORE3 (U(1) << 8) 51 #define INTERRUPT_PENDING_NONCPU (U(1) << 7) 52 #define INTERRUPT_PENDING_CRAIL (U(1) << 6) 53 #define INTERRUPT_PENDING_CORE0 (U(1) << 5) 54 #define INTERRUPT_PENDING_CORE1 (U(1) << 4) 55 #define INTERRUPT_PENDING_CORE2 (U(1) << 3) 56 #define INTERRUPT_PENDING_CORE3 (U(1) << 2) 57 #define CC4_INTERRUPT_PENDING (U(1) << 1) 58 #define HVC_INTERRUPT_PENDING (U(1) << 0) 59 #define FLOWCTRL_CC4_CORE0_CTRL (0x6cU) 60 #define FLOWCTRL_WAIT_WFI_BITMAP (0x100U) 61 #define FLOWCTRL_L2_FLUSH_CONTROL (0x94U) 62 #define FLOWCTRL_BPMP_CLUSTER_CONTROL (0x98U) 63 #define FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK (1U << 2) 64 65 #define FLOWCTRL_ENABLE_EXT 12U 66 #define FLOWCTRL_ENABLE_EXT_MASK 3U 67 #define FLOWCTRL_PG_CPU_NONCPU 0x1U 68 #define FLOWCTRL_TURNOFF_CPURAIL 0x2U 69 tegra_fc_read_32(uint32_t off)70static inline uint32_t tegra_fc_read_32(uint32_t off) 71 { 72 return mmio_read_32(TEGRA_FLOWCTRL_BASE + off); 73 } 74 tegra_fc_write_32(uint32_t off,uint32_t val)75static inline void tegra_fc_write_32(uint32_t off, uint32_t val) 76 { 77 mmio_write_32(TEGRA_FLOWCTRL_BASE + off, val); 78 } 79 80 void tegra_fc_bpmp_on(uint32_t entrypoint); 81 void tegra_fc_bpmp_off(void); 82 void tegra_fc_ccplex_pgexit_lock(void); 83 void tegra_fc_ccplex_pgexit_unlock(void); 84 void tegra_fc_cluster_idle(uint32_t midr); 85 void tegra_fc_cpu_powerdn(uint32_t mpidr); 86 void tegra_fc_cluster_powerdn(uint32_t midr); 87 void tegra_fc_cpu_on(int cpu); 88 void tegra_fc_cpu_off(int cpu); 89 void tegra_fc_disable_fiq_to_ccplex_routing(void); 90 void tegra_fc_enable_fiq_to_ccplex_routing(void); 91 bool tegra_fc_is_ccx_allowed(void); 92 void tegra_fc_lock_active_cluster(void); 93 void tegra_fc_soc_powerdn(uint32_t midr); 94 95 #endif /* FLOWCTRL_H */ 96