1 /*
2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <arch_helpers.h>
10 #include <bl31/bl31.h>
11 #include <bl31/interrupt_mgmt.h>
12 #include <common/bl_common.h>
13 #include <common/debug.h>
14 #include <common/interrupt_props.h>
15 #include <context.h>
16 #include <cortex_a57.h>
17 #include <denver.h>
18 #include <drivers/arm/gic_common.h>
19 #include <drivers/arm/gicv2.h>
20 #include <drivers/console.h>
21 #include <lib/el3_runtime/context_mgmt.h>
22 #include <lib/xlat_tables/xlat_tables_v2.h>
23 #include <plat/common/platform.h>
24
25 #include <mce.h>
26 #include <tegra_def.h>
27 #include <tegra_platform.h>
28 #include <tegra_private.h>
29
30 /*******************************************************************************
31 * Tegra186 CPU numbers in cluster #0
32 *******************************************************************************
33 */
34 #define TEGRA186_CLUSTER0_CORE2 2U
35 #define TEGRA186_CLUSTER0_CORE3 3U
36
37 /*******************************************************************************
38 * The Tegra power domain tree has a single system level power domain i.e. a
39 * single root node. The first entry in the power domain descriptor specifies
40 * the number of power domains at the highest power level.
41 *******************************************************************************
42 */
43 static const uint8_t tegra_power_domain_tree_desc[] = {
44 /* No of root nodes */
45 1,
46 /* No of clusters */
47 PLATFORM_CLUSTER_COUNT,
48 /* No of CPU cores - cluster0 */
49 PLATFORM_MAX_CPUS_PER_CLUSTER,
50 /* No of CPU cores - cluster1 */
51 PLATFORM_MAX_CPUS_PER_CLUSTER
52 };
53
54 /*******************************************************************************
55 * This function returns the Tegra default topology tree information.
56 ******************************************************************************/
plat_get_power_domain_tree_desc(void)57 const uint8_t *plat_get_power_domain_tree_desc(void)
58 {
59 return tegra_power_domain_tree_desc;
60 }
61
62 /*
63 * Table of regions to map using the MMU.
64 */
65 static const mmap_region_t tegra_mmap[] = {
66 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */
67 MT_DEVICE | MT_RW | MT_SECURE),
68 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */
69 MT_DEVICE | MT_RW | MT_SECURE),
70 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */
71 MT_DEVICE | MT_RW | MT_SECURE),
72 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */
73 MT_DEVICE | MT_RW | MT_SECURE),
74 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/
75 MT_DEVICE | MT_RW | MT_SECURE),
76 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */
77 MT_DEVICE | MT_RW | MT_SECURE),
78 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */
79 MT_DEVICE | MT_RW | MT_SECURE),
80 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */
81 MT_DEVICE | MT_RW | MT_SECURE),
82 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */
83 MT_DEVICE | MT_RW | MT_SECURE),
84 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */
85 MT_DEVICE | MT_RW | MT_SECURE),
86 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */
87 MT_DEVICE | MT_RW | MT_SECURE),
88 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */
89 MT_DEVICE | MT_RW | MT_SECURE),
90 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */
91 MT_DEVICE | MT_RW | MT_SECURE),
92 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */
93 MT_DEVICE | MT_RW | MT_SECURE),
94 MAP_REGION_FLAT(TEGRA_TMRUS_BASE, 0x1000U, /* 4KB */
95 MT_DEVICE | MT_RO | MT_SECURE),
96 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */
97 MT_DEVICE | MT_RW | MT_SECURE),
98 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */
99 MT_DEVICE | MT_RW | MT_SECURE),
100 MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000U, /* 128KB - ARM/Denver */
101 MT_DEVICE | MT_RW | MT_SECURE),
102 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000U, /* 64KB */
103 MT_DEVICE | MT_RW | MT_SECURE),
104 {0}
105 };
106
107 /*******************************************************************************
108 * Set up the pagetables as per the platform memory map & initialize the MMU
109 ******************************************************************************/
plat_get_mmio_map(void)110 const mmap_region_t *plat_get_mmio_map(void)
111 {
112 /* MMIO space */
113 return tegra_mmap;
114 }
115
116 /*******************************************************************************
117 * Handler to get the System Counter Frequency
118 ******************************************************************************/
plat_get_syscnt_freq2(void)119 uint32_t plat_get_syscnt_freq2(void)
120 {
121 return 31250000;
122 }
123
124 /*******************************************************************************
125 * Maximum supported UART controllers
126 ******************************************************************************/
127 #define TEGRA186_MAX_UART_PORTS 7
128
129 /*******************************************************************************
130 * This variable holds the UART port base addresses
131 ******************************************************************************/
132 static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
133 0, /* undefined - treated as an error case */
134 TEGRA_UARTA_BASE,
135 TEGRA_UARTB_BASE,
136 TEGRA_UARTC_BASE,
137 TEGRA_UARTD_BASE,
138 TEGRA_UARTE_BASE,
139 TEGRA_UARTF_BASE,
140 TEGRA_UARTG_BASE,
141 };
142
143 /*******************************************************************************
144 * Enable console corresponding to the console ID
145 ******************************************************************************/
plat_enable_console(int32_t id)146 void plat_enable_console(int32_t id)
147 {
148 static console_16550_t uart_console;
149 uint32_t console_clock;
150
151 if ((id > 0) && (id < TEGRA186_MAX_UART_PORTS)) {
152 /*
153 * Reference clock used by the FPGAs is a lot slower.
154 */
155 if (tegra_platform_is_fpga()) {
156 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
157 } else {
158 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
159 }
160
161 (void)console_16550_register(tegra186_uart_addresses[id],
162 console_clock,
163 TEGRA_CONSOLE_BAUDRATE,
164 &uart_console);
165 console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT |
166 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
167 }
168 }
169
170 /*******************************************************************************
171 * Handler for early platform setup
172 ******************************************************************************/
plat_early_platform_setup(void)173 void plat_early_platform_setup(void)
174 {
175 uint64_t impl, val;
176 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
177
178 /* sanity check MCE firmware compatibility */
179 mce_verify_firmware_version();
180
181 impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK;
182
183 /*
184 * Enable ECC and Parity Protection for Cortex-A57 CPUs (Tegra186
185 * A02p and beyond).
186 */
187 if ((plat_params->l2_ecc_parity_prot_dis != 1) &&
188 (impl != (uint64_t)DENVER_IMPL)) {
189
190 val = read_l2ctlr_el1();
191 val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
192 write_l2ctlr_el1(val);
193 }
194 }
195
196 /* Secure IRQs for Tegra186 */
197 static const interrupt_prop_t tegra186_interrupt_props[] = {
198 INTR_PROP_DESC(TEGRA186_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
199 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
200 INTR_PROP_DESC(TEGRA186_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
201 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
202 };
203
204 /*******************************************************************************
205 * Initialize the GIC and SGIs
206 ******************************************************************************/
plat_gic_setup(void)207 void plat_gic_setup(void)
208 {
209 tegra_gic_setup(tegra186_interrupt_props, ARRAY_SIZE(tegra186_interrupt_props));
210 tegra_gic_init();
211
212 /*
213 * Initialize the FIQ handler only if the platform supports any
214 * FIQ interrupt sources.
215 */
216 tegra_fiq_handler_setup();
217 }
218
219 /*******************************************************************************
220 * Return pointer to the BL31 params from previous bootloader
221 ******************************************************************************/
plat_get_bl31_params(void)222 struct tegra_bl31_params *plat_get_bl31_params(void)
223 {
224 uint32_t val;
225
226 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR);
227
228 return (struct tegra_bl31_params *)(uintptr_t)val;
229 }
230
231 /*******************************************************************************
232 * Return pointer to the BL31 platform params from previous bootloader
233 ******************************************************************************/
plat_get_bl31_plat_params(void)234 plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
235 {
236 uint32_t val;
237
238 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR);
239
240 return (plat_params_from_bl2_t *)(uintptr_t)val;
241 }
242
243 /*******************************************************************************
244 * This function implements a part of the critical interface between the psci
245 * generic layer and the platform that allows the former to query the platform
246 * to convert an MPIDR to a unique linear index. An error code (-1) is returned
247 * in case the MPIDR is invalid.
248 ******************************************************************************/
plat_core_pos_by_mpidr(u_register_t mpidr)249 int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
250 {
251 u_register_t cluster_id, cpu_id, pos;
252 int32_t ret;
253
254 cluster_id = (mpidr >> (u_register_t)MPIDR_AFF1_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
255 cpu_id = (mpidr >> (u_register_t)MPIDR_AFF0_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
256
257 /*
258 * Validate cluster_id by checking whether it represents
259 * one of the two clusters present on the platform.
260 * Validate cpu_id by checking whether it represents a CPU in
261 * one of the two clusters present on the platform.
262 */
263 if ((cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) ||
264 (cpu_id >= (u_register_t)PLATFORM_MAX_CPUS_PER_CLUSTER)) {
265 ret = PSCI_E_NOT_PRESENT;
266 } else {
267 /* calculate the core position */
268 pos = cpu_id + (cluster_id << 2U);
269
270 /* check for non-existent CPUs */
271 if ((pos == TEGRA186_CLUSTER0_CORE2) || (pos == TEGRA186_CLUSTER0_CORE3)) {
272 ret = PSCI_E_NOT_PRESENT;
273 } else {
274 ret = (int32_t)pos;
275 }
276 }
277
278 return ret;
279 }
280