1/* 2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <memctrl_v2.h> 11#include <plat/common/common_def.h> 12#include <tegra_def.h> 13 14#define TEGRA186_STATE_SYSTEM_SUSPEND 0x5C7 15#define TEGRA186_STATE_SYSTEM_RESUME 0x600D 16#define TEGRA186_SMMU_CTX_SIZE 0x420 17 18 .globl tegra186_cpu_reset_handler 19 20/* CPU reset handler routine */ 21func tegra186_cpu_reset_handler _align=4 22 /* check if we are exiting system suspend state */ 23 adr x0, __tegra186_system_suspend_state 24 ldr x1, [x0] 25 mov x2, #TEGRA186_STATE_SYSTEM_SUSPEND 26 lsl x2, x2, #16 27 add x2, x2, #TEGRA186_STATE_SYSTEM_SUSPEND 28 cmp x1, x2 29 bne boot_cpu 30 31 /* set system resume state */ 32 mov x1, #TEGRA186_STATE_SYSTEM_RESUME 33 lsl x1, x1, #16 34 mov x2, #TEGRA186_STATE_SYSTEM_RESUME 35 add x1, x1, x2 36 str x1, [x0] 37 dsb sy 38 39 /* prepare to relocate to TZSRAM */ 40 mov x0, #BL31_BASE 41 adr x1, __tegra186_cpu_reset_handler_end 42 adr x2, __tegra186_cpu_reset_handler_data 43 ldr x2, [x2, #8] 44 45 /* memcpy16 */ 46m_loop16: 47 cmp x2, #16 48 b.lt m_loop1 49 ldp x3, x4, [x1], #16 50 stp x3, x4, [x0], #16 51 sub x2, x2, #16 52 b m_loop16 53 /* copy byte per byte */ 54m_loop1: 55 cbz x2, boot_cpu 56 ldrb w3, [x1], #1 57 strb w3, [x0], #1 58 subs x2, x2, #1 59 b.ne m_loop1 60 61boot_cpu: 62 adr x0, __tegra186_cpu_reset_handler_data 63 ldr x0, [x0] 64 br x0 65endfunc tegra186_cpu_reset_handler 66 67 /* 68 * Tegra186 reset data (offset 0x0 - 0x430) 69 * 70 * 0x000: secure world's entrypoint 71 * 0x008: BL31 size (RO + RW) 72 * 0x00C: SMMU context start 73 * 0x42C: SMMU context end 74 */ 75 76 .align 4 77 .type __tegra186_cpu_reset_handler_data, %object 78 .globl __tegra186_cpu_reset_handler_data 79__tegra186_cpu_reset_handler_data: 80 .quad tegra_secure_entrypoint 81 .quad __BL31_END__ - BL31_BASE 82 83 .globl __tegra186_system_suspend_state 84__tegra186_system_suspend_state: 85 .quad 0 86 87 .align 4 88 .globl __tegra186_smmu_context 89__tegra186_smmu_context: 90 .rept TEGRA186_SMMU_CTX_SIZE 91 .quad 0 92 .endr 93 .size __tegra186_cpu_reset_handler_data, \ 94 . - __tegra186_cpu_reset_handler_data 95 96 .align 4 97 .globl __tegra186_cpu_reset_handler_end 98__tegra186_cpu_reset_handler_end: 99 100 .globl tegra186_get_cpu_reset_handler_size 101 .globl tegra186_get_cpu_reset_handler_base 102 .globl tegra186_get_smmu_ctx_offset 103 .globl tegra186_set_system_suspend_entry 104 105/* return size of the CPU reset handler */ 106func tegra186_get_cpu_reset_handler_size 107 adr x0, __tegra186_cpu_reset_handler_end 108 adr x1, tegra186_cpu_reset_handler 109 sub x0, x0, x1 110 ret 111endfunc tegra186_get_cpu_reset_handler_size 112 113/* return the start address of the CPU reset handler */ 114func tegra186_get_cpu_reset_handler_base 115 adr x0, tegra186_cpu_reset_handler 116 ret 117endfunc tegra186_get_cpu_reset_handler_base 118 119/* return the size of the SMMU context */ 120func tegra186_get_smmu_ctx_offset 121 adr x0, __tegra186_smmu_context 122 adr x1, tegra186_cpu_reset_handler 123 sub x0, x0, x1 124 ret 125endfunc tegra186_get_smmu_ctx_offset 126 127/* set system suspend state before SC7 entry */ 128func tegra186_set_system_suspend_entry 129 mov x0, #TEGRA_MC_BASE 130 mov x3, #MC_SECURITY_CFG3_0 131 ldr w1, [x0, x3] 132 lsl x1, x1, #32 133 mov x3, #MC_SECURITY_CFG0_0 134 ldr w2, [x0, x3] 135 orr x3, x1, x2 /* TZDRAM base */ 136 adr x0, __tegra186_system_suspend_state 137 adr x1, tegra186_cpu_reset_handler 138 sub x2, x0, x1 /* offset in TZDRAM */ 139 mov x0, #TEGRA186_STATE_SYSTEM_SUSPEND 140 lsl x0, x0, #16 141 add x0, x0, #TEGRA186_STATE_SYSTEM_SUSPEND 142 str x0, [x3, x2] /* set value in TZDRAM */ 143 dsb sy 144 ret 145endfunc tegra186_set_system_suspend_entry 146