1 /*
2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch_helpers.h>
12 #include <common/bl_common.h>
13 #include <common/debug.h>
14 #include <common/desc_image_load.h>
15 #include <lib/optee_utils.h>
16 #include <lib/xlat_tables/xlat_mmu_helpers.h>
17 #include <lib/xlat_tables/xlat_tables_defs.h>
18 #include <drivers/generic_delay_timer.h>
19 #include <drivers/rpi3/gpio/rpi3_gpio.h>
20 #include <drivers/rpi3/sdhost/rpi3_sdhost.h>
21
22 #include <rpi_shared.h>
23
24 /* Data structure which holds the extents of the trusted SRAM for BL2 */
25 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
26
27 /* rpi3 GPIO setup function. */
rpi3_gpio_setup(void)28 static void rpi3_gpio_setup(void)
29 {
30 struct rpi3_gpio_params params;
31
32 memset(¶ms, 0, sizeof(struct rpi3_gpio_params));
33 params.reg_base = RPI3_GPIO_BASE;
34
35 rpi3_gpio_init(¶ms);
36 }
37
38 /* Data structure which holds the MMC info */
39 static struct mmc_device_info mmc_info;
40
rpi3_sdhost_setup(void)41 static void rpi3_sdhost_setup(void)
42 {
43 struct rpi3_sdhost_params params;
44
45 memset(¶ms, 0, sizeof(struct rpi3_sdhost_params));
46 params.reg_base = RPI3_SDHOST_BASE;
47 params.bus_width = MMC_BUS_WIDTH_1;
48 params.clk_rate = 50000000;
49 mmc_info.mmc_dev_type = MMC_IS_SD_HC;
50 rpi3_sdhost_init(¶ms, &mmc_info);
51 }
52
53 /*******************************************************************************
54 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
55 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
56 * Copy it to a safe location before its reclaimed by later BL2 functionality.
57 ******************************************************************************/
58
bl2_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)59 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
60 u_register_t arg2, u_register_t arg3)
61 {
62 meminfo_t *mem_layout = (meminfo_t *) arg1;
63
64 /* Initialize the console to provide early debug support */
65 rpi3_console_init(PLAT_RPI3_UART_CLK_IN_HZ);
66
67 /* Enable arch timer */
68 generic_delay_timer_init();
69
70 /* Setup GPIO driver */
71 rpi3_gpio_setup();
72
73 /* Setup the BL2 memory layout */
74 bl2_tzram_layout = *mem_layout;
75
76 /* Setup SDHost driver */
77 rpi3_sdhost_setup();
78
79 plat_rpi3_io_setup();
80 }
81
bl2_platform_setup(void)82 void bl2_platform_setup(void)
83 {
84 /*
85 * This is where a TrustZone address space controller and other
86 * security related peripherals would be configured.
87 */
88 }
89
90 /*******************************************************************************
91 * Perform the very early platform specific architectural setup here.
92 ******************************************************************************/
bl2_plat_arch_setup(void)93 void bl2_plat_arch_setup(void)
94 {
95 rpi3_setup_page_tables(bl2_tzram_layout.total_base,
96 bl2_tzram_layout.total_size,
97 BL_CODE_BASE, BL_CODE_END,
98 BL_RO_DATA_BASE, BL_RO_DATA_END
99 #if USE_COHERENT_MEM
100 , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END
101 #endif
102 );
103
104 enable_mmu_el1(0);
105 }
106
107 /*******************************************************************************
108 * This function can be used by the platforms to update/use image
109 * information for given `image_id`.
110 ******************************************************************************/
bl2_plat_handle_post_image_load(unsigned int image_id)111 int bl2_plat_handle_post_image_load(unsigned int image_id)
112 {
113 int err = 0;
114 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
115 #ifdef SPD_opteed
116 bl_mem_params_node_t *pager_mem_params = NULL;
117 bl_mem_params_node_t *paged_mem_params = NULL;
118 #endif
119
120 assert(bl_mem_params != NULL);
121
122 switch (image_id) {
123 case BL32_IMAGE_ID:
124 #ifdef SPD_opteed
125 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
126 assert(pager_mem_params);
127
128 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
129 assert(paged_mem_params);
130
131 err = parse_optee_header(&bl_mem_params->ep_info,
132 &pager_mem_params->image_info,
133 &paged_mem_params->image_info);
134 if (err != 0)
135 WARN("OPTEE header parse error.\n");
136 #endif
137 bl_mem_params->ep_info.spsr = rpi3_get_spsr_for_bl32_entry();
138 break;
139
140 case BL33_IMAGE_ID:
141 /* BL33 expects to receive the primary CPU MPID (through r0) */
142 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
143 bl_mem_params->ep_info.spsr = rpi3_get_spsr_for_bl33_entry();
144
145 /* Shutting down the SDHost driver to let BL33 drives SDHost.*/
146 rpi3_sdhost_stop();
147 break;
148
149 default:
150 /* Do nothing in default case */
151 break;
152 }
153
154 return err;
155 }
156