1 // Copyright 2017 Google Inc. 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #ifndef CPU_FEATURES_INCLUDE_CPUINFO_ARM_H_ 16 #define CPU_FEATURES_INCLUDE_CPUINFO_ARM_H_ 17 18 #include <stdint.h> // uint32_t 19 #include "cpu_features_macros.h" 20 #include "cpu_features_cache_info.h" 21 22 CPU_FEATURES_START_CPP_NAMESPACE 23 24 typedef struct { 25 int swp : 1; // SWP instruction (atomic read-modify-write) 26 int half : 1; // Half-word loads and stores 27 int thumb : 1; // Thumb (16-bit instruction set) 28 int _26bit : 1; // "26 Bit" Model (Processor status register folded into program counter) 29 int fastmult : 1; // 32x32->64-bit multiplication 30 int fpa : 1; // Floating point accelerator 31 int vfp : 1; // Vector Floating Point. 32 int edsp : 1; // DSP extensions (the 'e' variant of the ARM9 CPUs, and all others above) 33 int java : 1; // Jazelle (Java bytecode accelerator) 34 int iwmmxt : 1; // Intel Wireless MMX Technology. 35 int crunch : 1; // MaverickCrunch coprocessor 36 int thumbee : 1; // ThumbEE 37 int neon : 1; // Advanced SIMD. 38 int vfpv3 : 1; // VFP version 3 39 int vfpv3d16 : 1; // VFP version 3 with 16 D-registers 40 int tls : 1; // TLS register 41 int vfpv4 : 1; // VFP version 4 with fast context switching 42 int idiva : 1; // SDIV and UDIV hardware division in ARM mode. 43 int idivt : 1; // SDIV and UDIV hardware division in Thumb mode. 44 int vfpd32 : 1; // VFP with 32 D-registers 45 int lpae : 1; // Large Physical Address Extension (>4GB physical memory on 32-bit architecture) 46 int evtstrm : 1; // kernel event stream using generic architected timer 47 int aes : 1; // Hardware-accelerated Advanced Encryption Standard. 48 int pmull : 1; // Polynomial multiply long. 49 int sha1 : 1; // Hardware-accelerated SHA1. 50 int sha2 : 1; // Hardware-accelerated SHA2-256. 51 int crc32 : 1; // Hardware-accelerated CRC-32. 52 53 // Make sure to update ArmFeaturesEnum below if you add a field here. 54 } ArmFeatures; 55 56 typedef struct { 57 ArmFeatures features; 58 int implementer; 59 int architecture; 60 int variant; 61 int part; 62 int revision; 63 } ArmInfo; 64 65 // TODO(user): Add macros to know which features are present at compile 66 // time. 67 68 ArmInfo GetArmInfo(void); 69 70 // Compute CpuId from ArmInfo. 71 uint32_t GetArmCpuId(const ArmInfo* const info); 72 73 //////////////////////////////////////////////////////////////////////////////// 74 // Introspection functions 75 76 typedef enum { 77 ARM_SWP, 78 ARM_HALF, 79 ARM_THUMB, 80 ARM_26BIT, 81 ARM_FASTMULT, 82 ARM_FPA, 83 ARM_VFP, 84 ARM_EDSP, 85 ARM_JAVA, 86 ARM_IWMMXT, 87 ARM_CRUNCH, 88 ARM_THUMBEE, 89 ARM_NEON, 90 ARM_VFPV3, 91 ARM_VFPV3D16, 92 ARM_TLS, 93 ARM_VFPV4, 94 ARM_IDIVA, 95 ARM_IDIVT, 96 ARM_VFPD32, 97 ARM_LPAE, 98 ARM_EVTSTRM, 99 ARM_AES, 100 ARM_PMULL, 101 ARM_SHA1, 102 ARM_SHA2, 103 ARM_CRC32, 104 ARM_LAST_, 105 } ArmFeaturesEnum; 106 107 int GetArmFeaturesEnumValue(const ArmFeatures* features, ArmFeaturesEnum value); 108 109 const char* GetArmFeaturesEnumName(ArmFeaturesEnum); 110 111 CPU_FEATURES_END_CPP_NAMESPACE 112 113 #if !defined(CPU_FEATURES_ARCH_ARM) 114 #error "Including cpuinfo_arm.h from a non-arm target." 115 #endif 116 117 #endif // CPU_FEATURES_INCLUDE_CPUINFO_ARM_H_ 118