1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #include <string.h>
34
35 #include "brw_context.h"
36 #include "brw_defines.h"
37 #include "brw_eu.h"
38
39 #include "ralloc.h"
40
41 /* Returns the corresponding conditional mod for swapping src0 and
42 * src1 in e.g. CMP.
43 */
44 uint32_t
brw_swap_cmod(uint32_t cmod)45 brw_swap_cmod(uint32_t cmod)
46 {
47 switch (cmod) {
48 case BRW_CONDITIONAL_Z:
49 case BRW_CONDITIONAL_NZ:
50 return cmod;
51 case BRW_CONDITIONAL_G:
52 return BRW_CONDITIONAL_L;
53 case BRW_CONDITIONAL_GE:
54 return BRW_CONDITIONAL_LE;
55 case BRW_CONDITIONAL_L:
56 return BRW_CONDITIONAL_G;
57 case BRW_CONDITIONAL_LE:
58 return BRW_CONDITIONAL_GE;
59 default:
60 return ~0;
61 }
62 }
63
64
65 /* How does predicate control work when execution_size != 8? Do I
66 * need to test/set for 0xffff when execution_size is 16?
67 */
brw_set_predicate_control_flag_value(struct brw_compile * p,unsigned value)68 void brw_set_predicate_control_flag_value( struct brw_compile *p, unsigned value )
69 {
70 p->current->header.predicate_control = BRW_PREDICATE_NONE;
71
72 if (value != 0xff) {
73 if (value != p->flag_value) {
74 brw_push_insn_state(p);
75 brw_MOV(p, brw_flag_reg(0, 0), brw_imm_uw(value));
76 p->flag_value = value;
77 brw_pop_insn_state(p);
78 }
79
80 p->current->header.predicate_control = BRW_PREDICATE_NORMAL;
81 }
82 }
83
brw_set_predicate_control(struct brw_compile * p,unsigned pc)84 void brw_set_predicate_control( struct brw_compile *p, unsigned pc )
85 {
86 p->current->header.predicate_control = pc;
87 }
88
brw_set_predicate_inverse(struct brw_compile * p,bool predicate_inverse)89 void brw_set_predicate_inverse(struct brw_compile *p, bool predicate_inverse)
90 {
91 p->current->header.predicate_inverse = predicate_inverse;
92 }
93
brw_set_conditionalmod(struct brw_compile * p,unsigned conditional)94 void brw_set_conditionalmod( struct brw_compile *p, unsigned conditional )
95 {
96 p->current->header.destreg__conditionalmod = conditional;
97 }
98
brw_set_flag_reg(struct brw_compile * p,int reg,int subreg)99 void brw_set_flag_reg(struct brw_compile *p, int reg, int subreg)
100 {
101 p->current->bits2.da1.flag_reg_nr = reg;
102 p->current->bits2.da1.flag_subreg_nr = subreg;
103 }
104
brw_set_access_mode(struct brw_compile * p,unsigned access_mode)105 void brw_set_access_mode( struct brw_compile *p, unsigned access_mode )
106 {
107 p->current->header.access_mode = access_mode;
108 }
109
110 void
brw_set_compression_control(struct brw_compile * p,enum brw_compression compression_control)111 brw_set_compression_control(struct brw_compile *p,
112 enum brw_compression compression_control)
113 {
114 p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
115
116 if (p->brw->intel.gen >= 6) {
117 /* Since we don't use the 32-wide support in gen6, we translate
118 * the pre-gen6 compression control here.
119 */
120 switch (compression_control) {
121 case BRW_COMPRESSION_NONE:
122 /* This is the "use the first set of bits of dmask/vmask/arf
123 * according to execsize" option.
124 */
125 p->current->header.compression_control = GEN6_COMPRESSION_1Q;
126 break;
127 case BRW_COMPRESSION_2NDHALF:
128 /* For 8-wide, this is "use the second set of 8 bits." */
129 p->current->header.compression_control = GEN6_COMPRESSION_2Q;
130 break;
131 case BRW_COMPRESSION_COMPRESSED:
132 /* For 16-wide instruction compression, use the first set of 16 bits
133 * since we don't do 32-wide dispatch.
134 */
135 p->current->header.compression_control = GEN6_COMPRESSION_1H;
136 break;
137 default:
138 assert(!"not reached");
139 p->current->header.compression_control = GEN6_COMPRESSION_1H;
140 break;
141 }
142 } else {
143 p->current->header.compression_control = compression_control;
144 }
145 }
146
brw_set_mask_control(struct brw_compile * p,unsigned value)147 void brw_set_mask_control( struct brw_compile *p, unsigned value )
148 {
149 p->current->header.mask_control = value;
150 }
151
brw_set_saturate(struct brw_compile * p,bool enable)152 void brw_set_saturate( struct brw_compile *p, bool enable )
153 {
154 p->current->header.saturate = enable;
155 }
156
brw_set_acc_write_control(struct brw_compile * p,unsigned value)157 void brw_set_acc_write_control(struct brw_compile *p, unsigned value)
158 {
159 if (p->brw->intel.gen >= 6)
160 p->current->header.acc_wr_control = value;
161 }
162
brw_push_insn_state(struct brw_compile * p)163 void brw_push_insn_state( struct brw_compile *p )
164 {
165 assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
166 memcpy(p->current+1, p->current, sizeof(struct brw_instruction));
167 p->compressed_stack[p->current - p->stack] = p->compressed;
168 p->current++;
169 }
170
brw_pop_insn_state(struct brw_compile * p)171 void brw_pop_insn_state( struct brw_compile *p )
172 {
173 assert(p->current != p->stack);
174 p->current--;
175 p->compressed = p->compressed_stack[p->current - p->stack];
176 }
177
178
179 /***********************************************************************
180 */
181 void
brw_init_compile(struct brw_context * brw,struct brw_compile * p,void * mem_ctx)182 brw_init_compile(struct brw_context *brw, struct brw_compile *p, void *mem_ctx)
183 {
184 memset(p, 0, sizeof(*p));
185
186 p->brw = brw;
187 /*
188 * Set the initial instruction store array size to 1024, if found that
189 * isn't enough, then it will double the store size at brw_next_insn()
190 * until out of memory.
191 */
192 p->store_size = 1024;
193 p->store = rzalloc_array(mem_ctx, struct brw_instruction, p->store_size);
194 p->nr_insn = 0;
195 p->current = p->stack;
196 p->compressed = false;
197 memset(p->current, 0, sizeof(p->current[0]));
198
199 p->mem_ctx = mem_ctx;
200
201 /* Some defaults?
202 */
203 brw_set_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
204 brw_set_saturate(p, 0);
205 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
206 brw_set_predicate_control_flag_value(p, 0xff);
207
208 /* Set up control flow stack */
209 p->if_stack_depth = 0;
210 p->if_stack_array_size = 16;
211 p->if_stack = rzalloc_array(mem_ctx, int, p->if_stack_array_size);
212
213 p->loop_stack_depth = 0;
214 p->loop_stack_array_size = 16;
215 p->loop_stack = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
216 p->if_depth_in_loop = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
217
218 brw_init_compaction_tables(&brw->intel);
219 }
220
221
brw_get_program(struct brw_compile * p,unsigned * sz)222 const unsigned *brw_get_program( struct brw_compile *p,
223 unsigned *sz )
224 {
225 brw_compact_instructions(p);
226
227 *sz = p->next_insn_offset;
228 return (const unsigned *)p->store;
229 }
230
231 void
brw_dump_compile(struct brw_compile * p,FILE * out,int start,int end)232 brw_dump_compile(struct brw_compile *p, FILE *out, int start, int end)
233 {
234 struct brw_context *brw = p->brw;
235 struct intel_context *intel = &brw->intel;
236 void *store = p->store;
237 bool dump_hex = false;
238
239 for (int offset = start; offset < end;) {
240 struct brw_instruction *insn = store + offset;
241 struct brw_instruction uncompacted;
242 printf("0x%08x: ", offset);
243
244 if (insn->header.cmpt_control) {
245 struct brw_compact_instruction *compacted = (void *)insn;
246 if (dump_hex) {
247 printf("0x%08x 0x%08x ",
248 ((uint32_t *)insn)[1],
249 ((uint32_t *)insn)[0]);
250 }
251
252 brw_uncompact_instruction(intel, &uncompacted, compacted);
253 insn = &uncompacted;
254 offset += 8;
255 } else {
256 if (dump_hex) {
257 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
258 ((uint32_t *)insn)[3],
259 ((uint32_t *)insn)[2],
260 ((uint32_t *)insn)[1],
261 ((uint32_t *)insn)[0]);
262 }
263 offset += 16;
264 }
265
266 brw_disasm(stdout, insn, p->brw->intel.gen);
267 }
268 }
269