1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "igt.h"
25 #include "drmtest.h"
26
27 #include <amdgpu.h>
28 #include <amdgpu_drm.h>
29
30 #define GFX_COMPUTE_NOP 0xffff1000
31 #define SDMA_NOP 0x0
32
33 static int
amdgpu_bo_alloc_and_map(amdgpu_device_handle dev,unsigned size,unsigned alignment,unsigned heap,uint64_t flags,amdgpu_bo_handle * bo,void ** cpu,uint64_t * mc_address,amdgpu_va_handle * va_handle)34 amdgpu_bo_alloc_and_map(amdgpu_device_handle dev, unsigned size,
35 unsigned alignment, unsigned heap, uint64_t flags,
36 amdgpu_bo_handle *bo, void **cpu, uint64_t *mc_address,
37 amdgpu_va_handle *va_handle)
38 {
39 struct amdgpu_bo_alloc_request request = {
40 .alloc_size = size,
41 .phys_alignment = alignment,
42 .preferred_heap = heap,
43 .flags = flags,
44 };
45 amdgpu_bo_handle buf_handle;
46 amdgpu_va_handle handle;
47 uint64_t vmc_addr;
48 int r;
49
50 r = amdgpu_bo_alloc(dev, &request, &buf_handle);
51 if (r)
52 return r;
53
54 r = amdgpu_va_range_alloc(dev,
55 amdgpu_gpu_va_range_general,
56 size, alignment, 0, &vmc_addr,
57 &handle, 0);
58 if (r)
59 goto error_va_alloc;
60
61 r = amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr, 0, AMDGPU_VA_OP_MAP);
62 if (r)
63 goto error_va_map;
64
65 r = amdgpu_bo_cpu_map(buf_handle, cpu);
66 if (r)
67 goto error_cpu_map;
68
69 *bo = buf_handle;
70 *mc_address = vmc_addr;
71 *va_handle = handle;
72
73 return 0;
74
75 error_cpu_map:
76 amdgpu_bo_cpu_unmap(buf_handle);
77
78 error_va_map:
79 amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP);
80
81 error_va_alloc:
82 amdgpu_bo_free(buf_handle);
83 return r;
84 }
85
86 static void
amdgpu_bo_unmap_and_free(amdgpu_bo_handle bo,amdgpu_va_handle va_handle,uint64_t mc_addr,uint64_t size)87 amdgpu_bo_unmap_and_free(amdgpu_bo_handle bo, amdgpu_va_handle va_handle,
88 uint64_t mc_addr, uint64_t size)
89 {
90 amdgpu_bo_cpu_unmap(bo);
91 amdgpu_bo_va_op(bo, 0, size, mc_addr, 0, AMDGPU_VA_OP_UNMAP);
92 amdgpu_va_range_free(va_handle);
93 amdgpu_bo_free(bo);
94 }
95
amdgpu_cs_sync(amdgpu_context_handle context,unsigned int ip_type,int ring,unsigned int seqno)96 static void amdgpu_cs_sync(amdgpu_context_handle context,
97 unsigned int ip_type,
98 int ring,
99 unsigned int seqno)
100 {
101 struct amdgpu_cs_fence fence = {
102 .context = context,
103 .ip_type = ip_type,
104 .ring = ring,
105 .fence = seqno,
106 };
107 uint32_t expired;
108 int err;
109
110 err = amdgpu_cs_query_fence_status(&fence,
111 AMDGPU_TIMEOUT_INFINITE,
112 0, &expired);
113 igt_assert_eq(err, 0);
114 }
115
116 #define SYNC 0x1
117 #define FORK 0x2
nop_cs(amdgpu_device_handle device,amdgpu_context_handle context,const char * name,unsigned int ip_type,unsigned int ring,unsigned int timeout,unsigned int flags)118 static void nop_cs(amdgpu_device_handle device,
119 amdgpu_context_handle context,
120 const char *name,
121 unsigned int ip_type,
122 unsigned int ring,
123 unsigned int timeout,
124 unsigned int flags)
125 {
126 const int ncpus = flags & FORK ? sysconf(_SC_NPROCESSORS_ONLN) : 1;
127 amdgpu_bo_handle ib_result_handle;
128 void *ib_result_cpu;
129 uint64_t ib_result_mc_address;
130 uint32_t *ptr;
131 int i, r;
132 amdgpu_bo_list_handle bo_list;
133 amdgpu_va_handle va_handle;
134
135 r = amdgpu_bo_alloc_and_map(device, 4096, 4096,
136 AMDGPU_GEM_DOMAIN_GTT, 0,
137 &ib_result_handle, &ib_result_cpu,
138 &ib_result_mc_address, &va_handle);
139 igt_assert_eq(r, 0);
140
141 ptr = ib_result_cpu;
142 for (i = 0; i < 16; ++i)
143 ptr[i] = GFX_COMPUTE_NOP;
144
145 r = amdgpu_bo_list_create(device, 1, &ib_result_handle, NULL, &bo_list);
146 igt_assert_eq(r, 0);
147
148 igt_fork(child, ncpus) {
149 struct amdgpu_cs_request ibs_request;
150 struct amdgpu_cs_ib_info ib_info;
151 struct timespec tv = {};
152 uint64_t submit_ns, sync_ns;
153 unsigned long count;
154
155 memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
156 ib_info.ib_mc_address = ib_result_mc_address;
157 ib_info.size = 16;
158
159 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
160 ibs_request.ip_type = ip_type;
161 ibs_request.ring = ring;
162 ibs_request.number_of_ibs = 1;
163 ibs_request.ibs = &ib_info;
164 ibs_request.resources = bo_list;
165
166 count = 0;
167 igt_nsec_elapsed(&tv);
168 igt_until_timeout(timeout) {
169 r = amdgpu_cs_submit(context, 0, &ibs_request, 1);
170 igt_assert_eq(r, 0);
171 if (flags & SYNC)
172 amdgpu_cs_sync(context, ip_type, ring,
173 ibs_request.seq_no);
174 count++;
175 }
176 submit_ns = igt_nsec_elapsed(&tv);
177
178 amdgpu_cs_sync(context, ip_type, ring, ibs_request.seq_no);
179 sync_ns = igt_nsec_elapsed(&tv);
180
181 igt_info("%s.%d: %'lu cycles, submit %.2fus, sync %.2fus\n",
182 name, child, count,
183 1e-3 * submit_ns / count, 1e-3 * sync_ns / count);
184 }
185 igt_waitchildren();
186
187 r = amdgpu_bo_list_destroy(bo_list);
188 igt_assert_eq(r, 0);
189
190 amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
191 ib_result_mc_address, 4096);
192 }
193
194 igt_main
195 {
196 amdgpu_device_handle device;
197 amdgpu_context_handle context;
198 const struct phase {
199 const char *name;
200 unsigned int flags;
201 } phase[] = {
202 { "nop", 0 },
203 { "sync", SYNC },
204 { "fork", FORK },
205 { "sync-fork", SYNC | FORK },
206 { },
207 }, *p;
208 const struct engine {
209 const char *name;
210 unsigned int ip_type;
211 } engines[] = {
212 { "compute", AMDGPU_HW_IP_COMPUTE },
213 { "gfx", AMDGPU_HW_IP_GFX },
214 { },
215 }, *e;
216 int fd = -1;
217
218 igt_fixture {
219 uint32_t major, minor;
220 int err;
221
222 fd = drm_open_driver(DRIVER_AMDGPU);
223
224 err = amdgpu_device_initialize(fd, &major, &minor, &device);
225 igt_require(err == 0);
226
227 err = amdgpu_cs_ctx_create(device, &context);
228 igt_assert_eq(err, 0);
229 }
230
231 for (p = phase; p->name; p++) {
232 for (e = engines; e->name; e++) {
233 igt_subtest_f("%s-%s0", p->name, e->name)
234 nop_cs(device, context, e->name, e->ip_type,
235 0, 20, p->flags);
236 }
237 }
238
239 igt_fixture {
240 amdgpu_cs_ctx_free(context);
241 amdgpu_device_deinitialize(device);
242 close(fd);
243 }
244 }
245