1 /*
2 * Copyright © 2011,2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Chris Wilson <chris@chris-wilson.co.uk>
25 * Daniel Vetter <daniel.vetter@ffwll.ch>
26 *
27 */
28
29 /*
30 * Testcase: Check whether we correctly invalidate the cs tlb
31 *
32 * Motivated by a strange bug on launchpad where *acth != ipehr, on snb notably
33 * where everything should be coherent by default.
34 *
35 * https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1063252
36 */
37
38 #include "igt.h"
39 #include <unistd.h>
40 #include <stdlib.h>
41 #include <stdint.h>
42 #include <stdio.h>
43 #include <string.h>
44 #include <fcntl.h>
45 #include <inttypes.h>
46 #include <errno.h>
47 #include <sys/stat.h>
48 #include <sys/ioctl.h>
49 #include <sys/time.h>
50
51 #include <drm.h>
52
53 IGT_TEST_DESCRIPTION("Check whether we correctly invalidate the cs tlb.");
54
55 #define LOCAL_I915_EXEC_VEBOX (4<<0)
56 #define EXEC_OBJECT_PINNED (1<<4)
57 #define BATCH_SIZE (1024*1024)
58
has_softpin(int fd)59 static bool has_softpin(int fd)
60 {
61 struct drm_i915_getparam gp;
62 int val = 0;
63
64 memset(&gp, 0, sizeof(gp));
65 gp.param = 37; /* I915_PARAM_HAS_EXEC_SOFTPIN */
66 gp.value = &val;
67
68 if (drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp))
69 return 0;
70
71 errno = 0;
72 return (val == 1);
73 }
74
75 static void *
mmap_coherent(int fd,uint32_t handle,int size)76 mmap_coherent(int fd, uint32_t handle, int size)
77 {
78 int domain;
79 void *ptr;
80
81 if (gem_has_llc(fd) || !gem_mmap__has_wc(fd)) {
82 domain = I915_GEM_DOMAIN_CPU;
83 ptr = gem_mmap__cpu(fd, handle, 0, size, PROT_WRITE);
84 } else {
85 domain = I915_GEM_DOMAIN_WC;
86 ptr = gem_mmap__wc(fd, handle, 0, size, PROT_WRITE);
87 }
88
89 gem_set_domain(fd, handle, domain, domain);
90 return ptr;
91 }
92
run_on_ring(int fd,unsigned ring_id,const char * ring_name)93 static void run_on_ring(int fd, unsigned ring_id, const char *ring_name)
94 {
95 struct drm_i915_gem_execbuffer2 execbuf;
96 struct drm_i915_gem_exec_object2 execobj;
97 struct {
98 uint32_t handle;
99 uint32_t *batch;
100 } obj[2];
101 unsigned i;
102 char buf[100];
103
104 gem_require_ring(fd, ring_id);
105 igt_require(has_softpin(fd));
106
107 for (i = 0; i < 2; i++) {
108 obj[i].handle = gem_create(fd, BATCH_SIZE);
109 obj[i].batch = mmap_coherent(fd, obj[i].handle, BATCH_SIZE);
110 memset(obj[i].batch, 0xff, BATCH_SIZE);
111 }
112
113 memset(&execobj, 0, sizeof(execobj));
114 execobj.handle = obj[0].handle;
115 obj[0].batch[0] = MI_BATCH_BUFFER_END;
116
117 memset(&execbuf, 0, sizeof(execbuf));
118 execbuf.buffers_ptr = to_user_pointer(&execobj);
119 execbuf.buffer_count = 1;
120 execbuf.flags = ring_id;
121
122 /* Execute once to allocate a gtt-offset */
123 gem_execbuf(fd, &execbuf);
124 execobj.flags = EXEC_OBJECT_PINNED;
125
126 sprintf(buf, "Testing %s cs tlb coherency: ", ring_name);
127 for (i = 0; i < BATCH_SIZE/64; i++) {
128 execobj.handle = obj[i&1].handle;
129 obj[i&1].batch[i*64/4] = MI_BATCH_BUFFER_END;
130 execbuf.batch_start_offset = i*64;
131
132 gem_execbuf(fd, &execbuf);
133 }
134
135 for (i = 0; i < 2; i++) {
136 gem_close(fd, obj[i].handle);
137 munmap(obj[i].batch, BATCH_SIZE);
138 }
139 }
140
141 igt_main
142 {
143 const struct intel_execution_engine2 *e;
144 int fd = -1;
145
146 igt_skip_on_simulation();
147
148 igt_fixture {
149 fd = drm_open_driver(DRIVER_INTEL);
150 igt_require_gem(fd);
151 }
152
153 __for_each_physical_engine(fd, e)
154 igt_subtest_f("%s", e->name)
155 run_on_ring(fd, e->flags, e->name);
156
157 igt_fixture
158 close(fd);
159 }
160