1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Chris Wilson <chris@chris-wilson.co.uk>
25 *
26 */
27
28 #include <stdlib.h>
29 #include <string.h>
30 #include <inttypes.h>
31 #include <errno.h>
32
33 #include "igt.h"
34
35 IGT_TEST_DESCRIPTION("Test execbuf fence accounting.");
36
37 #define WIDTH 1024
38 #define HEIGHT 1024
39 #define OBJECT_SIZE (4*WIDTH*HEIGHT)
40
41 #define BATCH_SIZE 4096
42
43 #define MAX_FENCES 64
44
45 /*
46 * Testcase: execbuf fence accounting
47 *
48 * We had a bug where we were falsely accounting upon reservation already
49 * fenced buffers as occupying a fence register even if they did not require
50 * one for the batch.
51 *
52 * We aim to exercise this by performing a sequence of fenced BLT
53 * with 2*num_avail_fence buffers, but alternating which half are fenced in
54 * each command.
55 */
56
57 static uint32_t
tiled_bo_create(int fd)58 tiled_bo_create (int fd)
59 {
60 uint32_t handle;
61
62 handle = gem_create(fd, OBJECT_SIZE);
63
64 gem_set_tiling(fd, handle, I915_TILING_X, WIDTH*4);
65
66 return handle;
67 }
68
69 static uint32_t
batch_create(int fd)70 batch_create (int fd)
71 {
72 uint32_t buf[] = { MI_BATCH_BUFFER_END, 0 };
73 uint32_t batch_handle;
74
75 batch_handle = gem_create(fd, BATCH_SIZE);
76
77 gem_write(fd, batch_handle, 0, buf, sizeof(buf));
78
79 return batch_handle;
80 }
81
fill_reloc(struct drm_i915_gem_relocation_entry * reloc,uint32_t handle)82 static void fill_reloc(struct drm_i915_gem_relocation_entry *reloc, uint32_t handle)
83 {
84 reloc->offset = 2 * sizeof(uint32_t);
85 reloc->target_handle = handle;
86 reloc->read_domains = I915_GEM_DOMAIN_RENDER;
87 reloc->write_domain = 0;
88 }
89
90 #define BUSY_LOAD (1 << 0)
91 #define INTERRUPTIBLE (1 << 1)
92
run_test(int fd,int num_fences,int expected_errno,unsigned flags)93 static void run_test(int fd, int num_fences, int expected_errno,
94 unsigned flags)
95 {
96 struct drm_i915_gem_execbuffer2 execbuf[2];
97 struct drm_i915_gem_exec_object2 exec[2][2*MAX_FENCES+1];
98 struct drm_i915_gem_relocation_entry reloc[2*MAX_FENCES];
99
100 unsigned long count;
101 int i, n;
102
103 igt_assert(2*num_fences+1 <= ARRAY_SIZE(exec[0]));
104 igt_assert(2*num_fences <= ARRAY_SIZE(reloc));
105
106 memset(execbuf, 0, sizeof(execbuf));
107 memset(exec, 0, sizeof(exec));
108 memset(reloc, 0, sizeof(reloc));
109
110 for (n = 0; n < 2*num_fences; n++) {
111 uint32_t handle = tiled_bo_create(fd);
112 exec[1][2*num_fences - n-1].handle = exec[0][n].handle = handle;
113 fill_reloc(&reloc[n], handle);
114 }
115
116 for (i = 0; i < 2; i++) {
117 for (n = 0; n < num_fences; n++)
118 exec[i][n].flags = EXEC_OBJECT_NEEDS_FENCE;
119
120 exec[i][2*num_fences].handle = batch_create(fd);
121 exec[i][2*num_fences].relocs_ptr = to_user_pointer(reloc);
122 exec[i][2*num_fences].relocation_count = 2*num_fences;
123
124 execbuf[i].buffers_ptr = to_user_pointer(exec[i]);
125 execbuf[i].buffer_count = 2*num_fences+1;
126 execbuf[i].batch_len = 2*sizeof(uint32_t);
127 }
128
129 count = 0;
130 igt_until_timeout(2) {
131 for (i = 0; i < 2; i++) {
132 igt_spin_t *spin = NULL;
133
134 if (flags & BUSY_LOAD)
135 spin = __igt_spin_new(fd);
136
137 igt_while_interruptible(flags & INTERRUPTIBLE) {
138 igt_assert_eq(__gem_execbuf(fd, &execbuf[i]),
139 -expected_errno);
140 }
141
142 igt_spin_free(fd, spin);
143 gem_quiescent_gpu(fd);
144 }
145 count++;
146 }
147 igt_info("Completed %lu cycles\n", count);
148
149 /* Cleanup */
150 for (n = 0; n < 2*num_fences; n++)
151 gem_close(fd, exec[0][n].handle);
152
153 for (i = 0; i < 2; i++)
154 gem_close(fd, exec[i][2*num_fences].handle);
155 }
156
157 igt_main
158 {
159 uint32_t devid = 0;
160 unsigned int num_fences = 0;
161 int fd = -1;
162
163 igt_skip_on_simulation();
164
165 igt_fixture {
166 fd = drm_open_driver(DRIVER_INTEL);
167 igt_require_gem(fd);
168
169 num_fences = gem_available_fences(fd);
170 igt_assert(num_fences > 4);
171 igt_assert(num_fences <= MAX_FENCES);
172
173 devid = intel_get_drm_devid(fd);
174 }
175
176 igt_subtest("2-spare-fences")
177 run_test(fd, num_fences - 2, 0, 0);
178 for (unsigned flags = 0; flags < 4; flags++) {
179 igt_subtest_f("no-spare-fences%s%s",
180 flags & BUSY_LOAD ? "-busy" : "",
181 flags & INTERRUPTIBLE ? "-interruptible" : "")
182 run_test(fd, num_fences, 0, flags);
183 }
184 igt_subtest("too-many-fences")
185 run_test(fd, num_fences + 1, intel_gen(devid) >= 4 ? 0 : EDEADLK, 0);
186
187 igt_fixture
188 close(fd);
189 }
190