1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Chris Wilson <chris@chris-wilson.co.uk>
25 *
26 */
27
28 /** @file gen3_linear_render_blits.c
29 *
30 * This is a test of doing many blits, with a working set
31 * larger than the aperture size.
32 *
33 * The goal is to simply ensure the basics work.
34 */
35
36 #include "igt.h"
37 #include <stdlib.h>
38 #include <stdio.h>
39 #include <string.h>
40 #include <fcntl.h>
41 #include <inttypes.h>
42 #include <errno.h>
43 #include <sys/stat.h>
44 #include <sys/time.h>
45 #include <sys/ioctl.h>
46 #include "drm.h"
47
48 #include "i915_reg.h"
49
50 #define WIDTH 512
51 #define HEIGHT 512
52
pack_float(float f)53 static inline uint32_t pack_float(float f)
54 {
55 union {
56 uint32_t dw;
57 float f;
58 } u;
59 u.f = f;
60 return u.dw;
61 }
62
fill_reloc(struct drm_i915_gem_relocation_entry * reloc,uint32_t offset,uint32_t handle,uint32_t read_domain,uint32_t write_domain)63 static uint32_t fill_reloc(struct drm_i915_gem_relocation_entry *reloc,
64 uint32_t offset,
65 uint32_t handle,
66 uint32_t read_domain,
67 uint32_t write_domain)
68 {
69 reloc->target_handle = handle;
70 reloc->delta = 0;
71 reloc->offset = offset * sizeof(uint32_t);
72 reloc->presumed_offset = 0;
73 reloc->read_domains = read_domain;
74 reloc->write_domain = write_domain;
75
76 return reloc->presumed_offset + reloc->delta;
77 }
78
79 static void
copy(int fd,uint32_t dst,uint32_t src)80 copy(int fd, uint32_t dst, uint32_t src)
81 {
82 uint32_t batch[1024], *b = batch;
83 struct drm_i915_gem_relocation_entry reloc[2], *r = reloc;
84 struct drm_i915_gem_exec_object2 obj[3];
85 struct drm_i915_gem_execbuffer2 exec;
86 uint32_t handle;
87
88 /* invariant state */
89 *b++ = (_3DSTATE_AA_CMD |
90 AA_LINE_ECAAR_WIDTH_ENABLE |
91 AA_LINE_ECAAR_WIDTH_1_0 |
92 AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
93 *b++ = (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
94 IAB_MODIFY_ENABLE |
95 IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
96 IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE <<
97 IAB_SRC_FACTOR_SHIFT) |
98 IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO <<
99 IAB_DST_FACTOR_SHIFT));
100 *b++ = (_3DSTATE_DFLT_DIFFUSE_CMD);
101 *b++ = (0);
102 *b++ = (_3DSTATE_DFLT_SPEC_CMD);
103 *b++ = (0);
104 *b++ = (_3DSTATE_DFLT_Z_CMD);
105 *b++ = (0);
106 *b++ = (_3DSTATE_COORD_SET_BINDINGS |
107 CSB_TCB(0, 0) |
108 CSB_TCB(1, 1) |
109 CSB_TCB(2, 2) |
110 CSB_TCB(3, 3) |
111 CSB_TCB(4, 4) |
112 CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
113 *b++ = (_3DSTATE_RASTER_RULES_CMD |
114 ENABLE_POINT_RASTER_RULE |
115 OGL_POINT_RASTER_RULE |
116 ENABLE_LINE_STRIP_PROVOKE_VRTX |
117 ENABLE_TRI_FAN_PROVOKE_VRTX |
118 LINE_STRIP_PROVOKE_VRTX(1) |
119 TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);
120 *b++ = (_3DSTATE_MODES_4_CMD |
121 ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
122 ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
123 ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
124 *b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2);
125 *b++ = (0x00000000); /* Disable texture coordinate wrap-shortest */
126 *b++ = ((1 << S4_POINT_WIDTH_SHIFT) |
127 S4_LINE_WIDTH_ONE |
128 S4_CULLMODE_NONE |
129 S4_VFMT_XY);
130 *b++ = (0x00000000); /* Stencil. */
131 *b++ = (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
132 *b++ = (_3DSTATE_SCISSOR_RECT_0_CMD);
133 *b++ = (0);
134 *b++ = (0);
135 *b++ = (_3DSTATE_DEPTH_SUBRECT_DISABLE);
136 *b++ = (_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
137 *b++ = (0);
138 *b++ = (_3DSTATE_STIPPLE);
139 *b++ = (0x00000000);
140 *b++ = (_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
141
142 /* samler state */
143 #define TEX_COUNT 1
144 *b++ = (_3DSTATE_MAP_STATE | (3 * TEX_COUNT));
145 *b++ = ((1 << TEX_COUNT) - 1);
146 *b = fill_reloc(r++, b-batch, src, I915_GEM_DOMAIN_SAMPLER, 0); b++;
147 *b++ = (MAPSURF_32BIT | MT_32BIT_ARGB8888 |
148 MS3_TILED_SURFACE |
149 (HEIGHT - 1) << MS3_HEIGHT_SHIFT |
150 (WIDTH - 1) << MS3_WIDTH_SHIFT);
151 *b++ = ((WIDTH-1) << MS4_PITCH_SHIFT);
152
153 *b++ = (_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT));
154 *b++ = ((1 << TEX_COUNT) - 1);
155 *b++ = (MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT |
156 FILTER_NEAREST << SS2_MAG_FILTER_SHIFT |
157 FILTER_NEAREST << SS2_MIN_FILTER_SHIFT);
158 *b++ = (TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT |
159 TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT |
160 0 << SS3_TEXTUREMAP_INDEX_SHIFT);
161 *b++ = (0x00000000);
162
163 /* render target state */
164 *b++ = (_3DSTATE_BUF_INFO_CMD);
165 *b++ = (BUF_3D_ID_COLOR_BACK | BUF_3D_TILED_SURFACE | WIDTH*4);
166 *b = fill_reloc(r++, b-batch, dst,
167 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
168 b++;
169
170 *b++ = (_3DSTATE_DST_BUF_VARS_CMD);
171 *b++ = (COLR_BUF_ARGB8888 |
172 DSTORG_HORT_BIAS(0x8) |
173 DSTORG_VERT_BIAS(0x8));
174
175 /* draw rect is unconditional */
176 *b++ = (_3DSTATE_DRAW_RECT_CMD);
177 *b++ = (0x00000000);
178 *b++ = (0x00000000); /* ymin, xmin */
179 *b++ = (DRAW_YMAX(HEIGHT - 1) |
180 DRAW_XMAX(WIDTH - 1));
181 /* yorig, xorig (relate to color buffer?) */
182 *b++ = (0x00000000);
183
184 /* texfmt */
185 *b++ = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(1) | I1_LOAD_S(2) | I1_LOAD_S(6) | 2);
186 *b++ = ((4 << S1_VERTEX_WIDTH_SHIFT) | (4 << S1_VERTEX_PITCH_SHIFT));
187 *b++ = (~S2_TEXCOORD_FMT(0, TEXCOORDFMT_NOT_PRESENT) |
188 S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D));
189 *b++ = (S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE |
190 BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT |
191 BLENDFACT_ONE << S6_CBUF_SRC_BLEND_FACT_SHIFT |
192 BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT);
193
194 /* pixel shader */
195 *b++ = (_3DSTATE_PIXEL_SHADER_PROGRAM | (1 + 3*3 - 2));
196 /* decl FS_T0 */
197 *b++ = (D0_DCL |
198 REG_TYPE(FS_T0) << D0_TYPE_SHIFT |
199 REG_NR(FS_T0) << D0_NR_SHIFT |
200 ((REG_TYPE(FS_T0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
201 *b++ = (0);
202 *b++ = (0);
203 /* decl FS_S0 */
204 *b++ = (D0_DCL |
205 (REG_TYPE(FS_S0) << D0_TYPE_SHIFT) |
206 (REG_NR(FS_S0) << D0_NR_SHIFT) |
207 ((REG_TYPE(FS_S0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0));
208 *b++ = (0);
209 *b++ = (0);
210 /* texld(FS_OC, FS_S0, FS_T0 */
211 *b++ = (T0_TEXLD |
212 (REG_TYPE(FS_OC) << T0_DEST_TYPE_SHIFT) |
213 (REG_NR(FS_OC) << T0_DEST_NR_SHIFT) |
214 (REG_NR(FS_S0) << T0_SAMPLER_NR_SHIFT));
215 *b++ = ((REG_TYPE(FS_T0) << T1_ADDRESS_REG_TYPE_SHIFT) |
216 (REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT));
217 *b++ = (0);
218
219 *b++ = (PRIM3D_RECTLIST | (3*4 - 1));
220 *b++ = pack_float(WIDTH);
221 *b++ = pack_float(HEIGHT);
222 *b++ = pack_float(WIDTH);
223 *b++ = pack_float(HEIGHT);
224
225 *b++ = pack_float(0);
226 *b++ = pack_float(HEIGHT);
227 *b++ = pack_float(0);
228 *b++ = pack_float(HEIGHT);
229
230 *b++ = pack_float(0);
231 *b++ = pack_float(0);
232 *b++ = pack_float(0);
233 *b++ = pack_float(0);
234
235 *b++ = MI_BATCH_BUFFER_END;
236 if ((b - batch) & 1)
237 *b++ = 0;
238
239 igt_assert(b - batch <= 1024);
240 handle = gem_create(fd, 4096);
241 gem_write(fd, handle, 0, batch, (b-batch)*sizeof(batch[0]));
242
243 igt_assert(r-reloc == 2);
244
245 obj[0].handle = dst;
246 obj[0].relocation_count = 0;
247 obj[0].relocs_ptr = 0;
248 obj[0].alignment = 0;
249 obj[0].offset = 0;
250 obj[0].flags = 0;
251 obj[0].rsvd1 = 0;
252 obj[0].rsvd2 = 0;
253
254 obj[1].handle = src;
255 obj[1].relocation_count = 0;
256 obj[1].relocs_ptr = 0;
257 obj[1].alignment = 0;
258 obj[1].offset = 0;
259 obj[1].flags = 0;
260 obj[1].rsvd1 = 0;
261 obj[1].rsvd2 = 0;
262
263 obj[2].handle = handle;
264 obj[2].relocation_count = 2;
265 obj[2].relocs_ptr = (uintptr_t)reloc;
266 obj[2].alignment = 0;
267 obj[2].offset = 0;
268 obj[2].flags = 0;
269 obj[2].rsvd1 = obj[2].rsvd2 = 0;
270
271 exec.buffers_ptr = (uintptr_t)obj;
272 exec.buffer_count = 3;
273 exec.batch_start_offset = 0;
274 exec.batch_len = (b-batch)*sizeof(batch[0]);
275 exec.DR1 = exec.DR4 = 0;
276 exec.num_cliprects = 0;
277 exec.cliprects_ptr = 0;
278 exec.flags = 0;
279 i915_execbuffer2_set_context_id(exec, 0);
280 exec.rsvd2 = 0;
281
282 gem_execbuf(fd, &exec);
283
284 gem_close(fd, handle);
285 }
286
287 static uint32_t
create_bo(int fd,uint32_t val)288 create_bo(int fd, uint32_t val)
289 {
290 uint32_t handle;
291 uint32_t *v;
292 int i;
293
294 handle = gem_create(fd, WIDTH*HEIGHT*4);
295 gem_set_tiling(fd, handle, I915_TILING_X, WIDTH*4);
296
297 /* Fill the BO with dwords starting at val */
298 v = gem_mmap__gtt(fd, handle, WIDTH * HEIGHT * 4,
299 PROT_READ | PROT_WRITE);
300 gem_set_domain(fd, handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
301 for (i = 0; i < WIDTH*HEIGHT; i++)
302 v[i] = val++;
303 munmap(v, WIDTH*HEIGHT*4);
304
305 return handle;
306 }
307
308 static void
check_bo(int fd,uint32_t handle,uint32_t val)309 check_bo(int fd, uint32_t handle, uint32_t val)
310 {
311 uint32_t *v;
312 int i;
313
314 v = gem_mmap__gtt(fd, handle, WIDTH * HEIGHT * 4, PROT_READ);
315 gem_set_domain(fd, handle, I915_GEM_DOMAIN_GTT, 0);
316 for (i = 0; i < WIDTH*HEIGHT; i++) {
317 igt_assert_f(v[i] == val,
318 "Expected 0x%08x, found 0x%08x "
319 "at offset 0x%08x\n",
320 val, v[i], i * 4);
321 val++;
322 }
323 munmap(v, WIDTH*HEIGHT*4);
324 }
325
326 int count;
327
opt_handler(int opt,int opt_index,void * data)328 static int opt_handler(int opt, int opt_index, void *data)
329 {
330 switch (opt) {
331 case 'c':
332 count = atoi(optarg);
333 break;
334 default:
335 return IGT_OPT_HANDLER_ERROR;
336 }
337
338 return IGT_OPT_HANDLER_SUCCESS;
339 }
340
341 const char *help_str = " -c\tBuffer count\n";
342
343 igt_simple_main_args("c:", NULL, help_str, opt_handler, NULL)
344 {
345 uint32_t *handle, *start_val;
346 uint32_t start = 0;
347 int i, fd;
348
349 fd = drm_open_driver(DRIVER_INTEL);
350
351 igt_require(IS_GEN3(intel_get_drm_devid(fd)));
352
353 if (count == 0)
354 count = 3 * gem_aperture_size(fd) / (1024*1024) / 2;
355 igt_info("Using %d 1MiB buffers\n", count);
356 intel_require_memory(count, 1024*1024, CHECK_RAM);
357
358 handle = malloc(sizeof(uint32_t)*count*2);
359 start_val = handle + count;
360
361 for (i = 0; i < count; i++) {
362 handle[i] = create_bo(fd, start);
363 start_val[i] = start;
364 start += 1024 * 1024 / 4;
365 }
366
367 igt_info("Verifying initialisation...\n");
368 for (i = 0; i < count; i++)
369 check_bo(fd, handle[i], start_val[i]);
370
371 igt_info("Cyclic blits, forward...\n");
372 for (i = 0; i < count * 4; i++) {
373 int src = i % count;
374 int dst = (i + 1) % count;
375
376 copy(fd, handle[dst], handle[src]);
377 start_val[dst] = start_val[src];
378 }
379 for (i = 0; i < count; i++)
380 check_bo(fd, handle[i], start_val[i]);
381
382 igt_info("Cyclic blits, backward...\n");
383 for (i = 0; i < count * 4; i++) {
384 int src = (i + 1) % count;
385 int dst = i % count;
386
387 copy(fd, handle[dst], handle[src]);
388 start_val[dst] = start_val[src];
389 }
390 for (i = 0; i < count; i++)
391 check_bo(fd, handle[i], start_val[i]);
392
393 igt_info("Random blits...\n");
394 for (i = 0; i < count * 4; i++) {
395 int src = random() % count;
396 int dst = random() % count;
397
398 if (src == dst)
399 continue;
400
401 copy(fd, handle[dst], handle[src]);
402 start_val[dst] = start_val[src];
403 }
404 for (i = 0; i < count; i++)
405 check_bo(fd, handle[i], start_val[i]);
406 }
407