1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * IOMMU user API definitions 4 */ 5 6 #ifndef _UAPI_IOMMU_H 7 #define _UAPI_IOMMU_H 8 9 #include <linux/types.h> 10 11 #define IOMMU_FAULT_PERM_READ (1 << 0) /* read */ 12 #define IOMMU_FAULT_PERM_WRITE (1 << 1) /* write */ 13 #define IOMMU_FAULT_PERM_EXEC (1 << 2) /* exec */ 14 #define IOMMU_FAULT_PERM_PRIV (1 << 3) /* privileged */ 15 16 /* Generic fault types, can be expanded IRQ remapping fault */ 17 enum iommu_fault_type { 18 IOMMU_FAULT_DMA_UNRECOV = 1, /* unrecoverable fault */ 19 IOMMU_FAULT_PAGE_REQ, /* page request fault */ 20 }; 21 22 enum iommu_fault_reason { 23 IOMMU_FAULT_REASON_UNKNOWN = 0, 24 25 /* Could not access the PASID table (fetch caused external abort) */ 26 IOMMU_FAULT_REASON_PASID_FETCH, 27 28 /* PASID entry is invalid or has configuration errors */ 29 IOMMU_FAULT_REASON_BAD_PASID_ENTRY, 30 31 /* 32 * PASID is out of range (e.g. exceeds the maximum PASID 33 * supported by the IOMMU) or disabled. 34 */ 35 IOMMU_FAULT_REASON_PASID_INVALID, 36 37 /* 38 * An external abort occurred fetching (or updating) a translation 39 * table descriptor 40 */ 41 IOMMU_FAULT_REASON_WALK_EABT, 42 43 /* 44 * Could not access the page table entry (Bad address), 45 * actual translation fault 46 */ 47 IOMMU_FAULT_REASON_PTE_FETCH, 48 49 /* Protection flag check failed */ 50 IOMMU_FAULT_REASON_PERMISSION, 51 52 /* access flag check failed */ 53 IOMMU_FAULT_REASON_ACCESS, 54 55 /* Output address of a translation stage caused Address Size fault */ 56 IOMMU_FAULT_REASON_OOR_ADDRESS, 57 }; 58 59 /** 60 * struct iommu_fault_unrecoverable - Unrecoverable fault data 61 * @reason: reason of the fault, from &enum iommu_fault_reason 62 * @flags: parameters of this fault (IOMMU_FAULT_UNRECOV_* values) 63 * @pasid: Process Address Space ID 64 * @perm: requested permission access using by the incoming transaction 65 * (IOMMU_FAULT_PERM_* values) 66 * @addr: offending page address 67 * @fetch_addr: address that caused a fetch abort, if any 68 */ 69 struct iommu_fault_unrecoverable { 70 __u32 reason; 71 #define IOMMU_FAULT_UNRECOV_PASID_VALID (1 << 0) 72 #define IOMMU_FAULT_UNRECOV_ADDR_VALID (1 << 1) 73 #define IOMMU_FAULT_UNRECOV_FETCH_ADDR_VALID (1 << 2) 74 __u32 flags; 75 __u32 pasid; 76 __u32 perm; 77 __u64 addr; 78 __u64 fetch_addr; 79 }; 80 81 /** 82 * struct iommu_fault_page_request - Page Request data 83 * @flags: encodes whether the corresponding fields are valid and whether this 84 * is the last page in group (IOMMU_FAULT_PAGE_REQUEST_* values) 85 * @pasid: Process Address Space ID 86 * @grpid: Page Request Group Index 87 * @perm: requested page permissions (IOMMU_FAULT_PERM_* values) 88 * @addr: page address 89 * @private_data: device-specific private information 90 */ 91 struct iommu_fault_page_request { 92 #define IOMMU_FAULT_PAGE_REQUEST_PASID_VALID (1 << 0) 93 #define IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE (1 << 1) 94 #define IOMMU_FAULT_PAGE_REQUEST_PRIV_DATA (1 << 2) 95 __u32 flags; 96 __u32 pasid; 97 __u32 grpid; 98 __u32 perm; 99 __u64 addr; 100 __u64 private_data[2]; 101 }; 102 103 /** 104 * struct iommu_fault - Generic fault data 105 * @type: fault type from &enum iommu_fault_type 106 * @padding: reserved for future use (should be zero) 107 * @event: fault event, when @type is %IOMMU_FAULT_DMA_UNRECOV 108 * @prm: Page Request message, when @type is %IOMMU_FAULT_PAGE_REQ 109 * @padding2: sets the fault size to allow for future extensions 110 */ 111 struct iommu_fault { 112 __u32 type; 113 __u32 padding; 114 union { 115 struct iommu_fault_unrecoverable event; 116 struct iommu_fault_page_request prm; 117 __u8 padding2[56]; 118 }; 119 }; 120 121 /** 122 * enum iommu_page_response_code - Return status of fault handlers 123 * @IOMMU_PAGE_RESP_SUCCESS: Fault has been handled and the page tables 124 * populated, retry the access. This is "Success" in PCI PRI. 125 * @IOMMU_PAGE_RESP_FAILURE: General error. Drop all subsequent faults from 126 * this device if possible. This is "Response Failure" in PCI PRI. 127 * @IOMMU_PAGE_RESP_INVALID: Could not handle this fault, don't retry the 128 * access. This is "Invalid Request" in PCI PRI. 129 */ 130 enum iommu_page_response_code { 131 IOMMU_PAGE_RESP_SUCCESS = 0, 132 IOMMU_PAGE_RESP_INVALID, 133 IOMMU_PAGE_RESP_FAILURE, 134 }; 135 136 /** 137 * struct iommu_page_response - Generic page response information 138 * @version: API version of this structure 139 * @flags: encodes whether the corresponding fields are valid 140 * (IOMMU_FAULT_PAGE_RESPONSE_* values) 141 * @pasid: Process Address Space ID 142 * @grpid: Page Request Group Index 143 * @code: response code from &enum iommu_page_response_code 144 */ 145 struct iommu_page_response { 146 #define IOMMU_PAGE_RESP_VERSION_1 1 147 __u32 version; 148 #define IOMMU_PAGE_RESP_PASID_VALID (1 << 0) 149 __u32 flags; 150 __u32 pasid; 151 __u32 grpid; 152 __u32 code; 153 }; 154 155 /* defines the granularity of the invalidation */ 156 enum iommu_inv_granularity { 157 IOMMU_INV_GRANU_DOMAIN, /* domain-selective invalidation */ 158 IOMMU_INV_GRANU_PASID, /* PASID-selective invalidation */ 159 IOMMU_INV_GRANU_ADDR, /* page-selective invalidation */ 160 IOMMU_INV_GRANU_NR, /* number of invalidation granularities */ 161 }; 162 163 /** 164 * struct iommu_inv_addr_info - Address Selective Invalidation Structure 165 * 166 * @flags: indicates the granularity of the address-selective invalidation 167 * - If the PASID bit is set, the @pasid field is populated and the invalidation 168 * relates to cache entries tagged with this PASID and matching the address 169 * range. 170 * - If ARCHID bit is set, @archid is populated and the invalidation relates 171 * to cache entries tagged with this architecture specific ID and matching 172 * the address range. 173 * - Both PASID and ARCHID can be set as they may tag different caches. 174 * - If neither PASID or ARCHID is set, global addr invalidation applies. 175 * - The LEAF flag indicates whether only the leaf PTE caching needs to be 176 * invalidated and other paging structure caches can be preserved. 177 * @pasid: process address space ID 178 * @archid: architecture-specific ID 179 * @addr: first stage/level input address 180 * @granule_size: page/block size of the mapping in bytes 181 * @nb_granules: number of contiguous granules to be invalidated 182 */ 183 struct iommu_inv_addr_info { 184 #define IOMMU_INV_ADDR_FLAGS_PASID (1 << 0) 185 #define IOMMU_INV_ADDR_FLAGS_ARCHID (1 << 1) 186 #define IOMMU_INV_ADDR_FLAGS_LEAF (1 << 2) 187 __u32 flags; 188 __u32 archid; 189 __u64 pasid; 190 __u64 addr; 191 __u64 granule_size; 192 __u64 nb_granules; 193 }; 194 195 /** 196 * struct iommu_inv_pasid_info - PASID Selective Invalidation Structure 197 * 198 * @flags: indicates the granularity of the PASID-selective invalidation 199 * - If the PASID bit is set, the @pasid field is populated and the invalidation 200 * relates to cache entries tagged with this PASID and matching the address 201 * range. 202 * - If the ARCHID bit is set, the @archid is populated and the invalidation 203 * relates to cache entries tagged with this architecture specific ID and 204 * matching the address range. 205 * - Both PASID and ARCHID can be set as they may tag different caches. 206 * - At least one of PASID or ARCHID must be set. 207 * @pasid: process address space ID 208 * @archid: architecture-specific ID 209 */ 210 struct iommu_inv_pasid_info { 211 #define IOMMU_INV_PASID_FLAGS_PASID (1 << 0) 212 #define IOMMU_INV_PASID_FLAGS_ARCHID (1 << 1) 213 __u32 flags; 214 __u32 archid; 215 __u64 pasid; 216 }; 217 218 /** 219 * struct iommu_cache_invalidate_info - First level/stage invalidation 220 * information 221 * @version: API version of this structure 222 * @cache: bitfield that allows to select which caches to invalidate 223 * @granularity: defines the lowest granularity used for the invalidation: 224 * domain > PASID > addr 225 * @padding: reserved for future use (should be zero) 226 * @pasid_info: invalidation data when @granularity is %IOMMU_INV_GRANU_PASID 227 * @addr_info: invalidation data when @granularity is %IOMMU_INV_GRANU_ADDR 228 * 229 * Not all the combinations of cache/granularity are valid: 230 * 231 * +--------------+---------------+---------------+---------------+ 232 * | type / | DEV_IOTLB | IOTLB | PASID | 233 * | granularity | | | cache | 234 * +==============+===============+===============+===============+ 235 * | DOMAIN | N/A | Y | Y | 236 * +--------------+---------------+---------------+---------------+ 237 * | PASID | Y | Y | Y | 238 * +--------------+---------------+---------------+---------------+ 239 * | ADDR | Y | Y | N/A | 240 * +--------------+---------------+---------------+---------------+ 241 * 242 * Invalidations by %IOMMU_INV_GRANU_DOMAIN don't take any argument other than 243 * @version and @cache. 244 * 245 * If multiple cache types are invalidated simultaneously, they all 246 * must support the used granularity. 247 */ 248 struct iommu_cache_invalidate_info { 249 #define IOMMU_CACHE_INVALIDATE_INFO_VERSION_1 1 250 __u32 version; 251 /* IOMMU paging structure cache */ 252 #define IOMMU_CACHE_INV_TYPE_IOTLB (1 << 0) /* IOMMU IOTLB */ 253 #define IOMMU_CACHE_INV_TYPE_DEV_IOTLB (1 << 1) /* Device IOTLB */ 254 #define IOMMU_CACHE_INV_TYPE_PASID (1 << 2) /* PASID cache */ 255 #define IOMMU_CACHE_INV_TYPE_NR (3) 256 __u8 cache; 257 __u8 granularity; 258 __u8 padding[2]; 259 union { 260 struct iommu_inv_pasid_info pasid_info; 261 struct iommu_inv_addr_info addr_info; 262 }; 263 }; 264 265 /** 266 * struct iommu_gpasid_bind_data_vtd - Intel VT-d specific data on device and guest 267 * SVA binding. 268 * 269 * @flags: VT-d PASID table entry attributes 270 * @pat: Page attribute table data to compute effective memory type 271 * @emt: Extended memory type 272 * 273 * Only guest vIOMMU selectable and effective options are passed down to 274 * the host IOMMU. 275 */ 276 struct iommu_gpasid_bind_data_vtd { 277 #define IOMMU_SVA_VTD_GPASID_SRE (1 << 0) /* supervisor request */ 278 #define IOMMU_SVA_VTD_GPASID_EAFE (1 << 1) /* extended access enable */ 279 #define IOMMU_SVA_VTD_GPASID_PCD (1 << 2) /* page-level cache disable */ 280 #define IOMMU_SVA_VTD_GPASID_PWT (1 << 3) /* page-level write through */ 281 #define IOMMU_SVA_VTD_GPASID_EMTE (1 << 4) /* extended mem type enable */ 282 #define IOMMU_SVA_VTD_GPASID_CD (1 << 5) /* PASID-level cache disable */ 283 __u64 flags; 284 __u32 pat; 285 __u32 emt; 286 }; 287 288 /** 289 * struct iommu_gpasid_bind_data - Information about device and guest PASID binding 290 * @version: Version of this data structure 291 * @format: PASID table entry format 292 * @flags: Additional information on guest bind request 293 * @gpgd: Guest page directory base of the guest mm to bind 294 * @hpasid: Process address space ID used for the guest mm in host IOMMU 295 * @gpasid: Process address space ID used for the guest mm in guest IOMMU 296 * @addr_width: Guest virtual address width 297 * @padding: Reserved for future use (should be zero) 298 * @vtd: Intel VT-d specific data 299 * 300 * Guest to host PASID mapping can be an identity or non-identity, where guest 301 * has its own PASID space. For non-identify mapping, guest to host PASID lookup 302 * is needed when VM programs guest PASID into an assigned device. VMM may 303 * trap such PASID programming then request host IOMMU driver to convert guest 304 * PASID to host PASID based on this bind data. 305 */ 306 struct iommu_gpasid_bind_data { 307 #define IOMMU_GPASID_BIND_VERSION_1 1 308 __u32 version; 309 #define IOMMU_PASID_FORMAT_INTEL_VTD 1 310 __u32 format; 311 #define IOMMU_SVA_GPASID_VAL (1 << 0) /* guest PASID valid */ 312 __u64 flags; 313 __u64 gpgd; 314 __u64 hpasid; 315 __u64 gpasid; 316 __u32 addr_width; 317 __u8 padding[12]; 318 /* Vendor specific data */ 319 union { 320 struct iommu_gpasid_bind_data_vtd vtd; 321 }; 322 }; 323 324 #endif /* _UAPI_IOMMU_H */ 325