1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
15 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
16
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/Support/CodeGen.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23
24 #define GET_INSTRINFO_HEADER
25 #include "ARMGenInstrInfo.inc"
26
27 namespace llvm {
28 class ARMSubtarget;
29 class ARMBaseRegisterInfo;
30
31 class ARMBaseInstrInfo : public ARMGenInstrInfo {
32 const ARMSubtarget &Subtarget;
33
34 protected:
35 // Can be only subclassed.
36 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
37
38 void expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
39 unsigned LoadImmOpc, unsigned LoadOpc) const;
40
41 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
42 /// and \p DefIdx.
43 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
44 /// the list is modeled as <Reg:SubReg, SubIdx>.
45 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
46 /// two elements:
47 /// - vreg1:sub1, sub0
48 /// - vreg2<:0>, sub1
49 ///
50 /// \returns true if it is possible to build such an input sequence
51 /// with the pair \p MI, \p DefIdx. False otherwise.
52 ///
53 /// \pre MI.isRegSequenceLike().
54 bool getRegSequenceLikeInputs(
55 const MachineInstr &MI, unsigned DefIdx,
56 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
57
58 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
59 /// and \p DefIdx.
60 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
61 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
62 /// - vreg1:sub1, sub0
63 ///
64 /// \returns true if it is possible to build such an input sequence
65 /// with the pair \p MI, \p DefIdx. False otherwise.
66 ///
67 /// \pre MI.isExtractSubregLike().
68 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
69 RegSubRegPairAndIdx &InputReg) const override;
70
71 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
72 /// and \p DefIdx.
73 /// \p [out] BaseReg and \p [out] InsertedReg contain
74 /// the equivalent inputs of INSERT_SUBREG.
75 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
76 /// - BaseReg: vreg0:sub0
77 /// - InsertedReg: vreg1:sub1, sub3
78 ///
79 /// \returns true if it is possible to build such an input sequence
80 /// with the pair \p MI, \p DefIdx. False otherwise.
81 ///
82 /// \pre MI.isInsertSubregLike().
83 bool
84 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
85 RegSubRegPair &BaseReg,
86 RegSubRegPairAndIdx &InsertedReg) const override;
87
88 /// Commutes the operands in the given instruction.
89 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
90 ///
91 /// Do not call this method for a non-commutable instruction or for
92 /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
93 /// Even though the instruction is commutable, the method may still
94 /// fail to commute the operands, null pointer is returned in such cases.
95 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
96 unsigned OpIdx1,
97 unsigned OpIdx2) const override;
98
99 public:
100 // Return whether the target has an explicit NOP encoding.
101 bool hasNOP() const;
102
103 // Return the non-pre/post incrementing version of 'Opc'. Return 0
104 // if there is not such an opcode.
105 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
106
107 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
108 MachineInstr &MI,
109 LiveVariables *LV) const override;
110
111 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
getSubtarget()112 const ARMSubtarget &getSubtarget() const { return Subtarget; }
113
114 ScheduleHazardRecognizer *
115 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
116 const ScheduleDAG *DAG) const override;
117
118 ScheduleHazardRecognizer *
119 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
120 const ScheduleDAG *DAG) const override;
121
122 // Branch analysis.
123 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
124 MachineBasicBlock *&FBB,
125 SmallVectorImpl<MachineOperand> &Cond,
126 bool AllowModify = false) const override;
127 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
128 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
129 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
130 const DebugLoc &DL) const override;
131
132 bool
133 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
134
135 // Predication support.
136 bool isPredicated(const MachineInstr &MI) const override;
137
getPredicate(const MachineInstr & MI)138 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const {
139 int PIdx = MI.findFirstPredOperandIdx();
140 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
141 : ARMCC::AL;
142 }
143
144 bool PredicateInstruction(MachineInstr &MI,
145 ArrayRef<MachineOperand> Pred) const override;
146
147 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
148 ArrayRef<MachineOperand> Pred2) const override;
149
150 bool DefinesPredicate(MachineInstr &MI,
151 std::vector<MachineOperand> &Pred) const override;
152
153 bool isPredicable(MachineInstr &MI) const override;
154
155 /// GetInstSize - Returns the size of the specified MachineInstr.
156 ///
157 virtual unsigned GetInstSizeInBytes(const MachineInstr &MI) const;
158
159 unsigned isLoadFromStackSlot(const MachineInstr &MI,
160 int &FrameIndex) const override;
161 unsigned isStoreToStackSlot(const MachineInstr &MI,
162 int &FrameIndex) const override;
163 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
164 int &FrameIndex) const override;
165 unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
166 int &FrameIndex) const override;
167
168 void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
169 unsigned SrcReg, bool KillSrc,
170 const ARMSubtarget &Subtarget) const;
171 void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
172 unsigned DestReg, bool KillSrc,
173 const ARMSubtarget &Subtarget) const;
174
175 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
176 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
177 bool KillSrc) const override;
178
179 void storeRegToStackSlot(MachineBasicBlock &MBB,
180 MachineBasicBlock::iterator MBBI,
181 unsigned SrcReg, bool isKill, int FrameIndex,
182 const TargetRegisterClass *RC,
183 const TargetRegisterInfo *TRI) const override;
184
185 void loadRegFromStackSlot(MachineBasicBlock &MBB,
186 MachineBasicBlock::iterator MBBI,
187 unsigned DestReg, int FrameIndex,
188 const TargetRegisterClass *RC,
189 const TargetRegisterInfo *TRI) const override;
190
191 bool expandPostRAPseudo(MachineInstr &MI) const override;
192
193 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
194 unsigned DestReg, unsigned SubIdx,
195 const MachineInstr &Orig,
196 const TargetRegisterInfo &TRI) const override;
197
198 MachineInstr *duplicate(MachineInstr &Orig,
199 MachineFunction &MF) const override;
200
201 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
202 unsigned SubIdx, unsigned State,
203 const TargetRegisterInfo *TRI) const;
204
205 bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
206 const MachineRegisterInfo *MRI) const override;
207
208 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
209 /// determine if two loads are loading from the same base address. It should
210 /// only return true if the base pointers are the same and the only
211 /// differences between the two addresses is the offset. It also returns the
212 /// offsets by reference.
213 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
214 int64_t &Offset2) const override;
215
216 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
217 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
218 /// should be scheduled togther. On some targets if two loads are loading from
219 /// addresses in the same cache line, it's better if they are scheduled
220 /// together. This function takes two integers that represent the load offsets
221 /// from the common base address. It returns true if it decides it's desirable
222 /// to schedule the two loads together. "NumLoads" is the number of loads that
223 /// have already been scheduled after Load1.
224 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
225 int64_t Offset1, int64_t Offset2,
226 unsigned NumLoads) const override;
227
228 bool isSchedulingBoundary(const MachineInstr &MI,
229 const MachineBasicBlock *MBB,
230 const MachineFunction &MF) const override;
231
232 bool isProfitableToIfCvt(MachineBasicBlock &MBB,
233 unsigned NumCycles, unsigned ExtraPredCycles,
234 BranchProbability Probability) const override;
235
236 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
237 unsigned ExtraT, MachineBasicBlock &FMBB,
238 unsigned NumF, unsigned ExtraF,
239 BranchProbability Probability) const override;
240
isProfitableToDupForIfCvt(MachineBasicBlock & MBB,unsigned NumCycles,BranchProbability Probability)241 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
242 BranchProbability Probability) const override {
243 return NumCycles == 1;
244 }
245
246 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
247 MachineBasicBlock &FMBB) const override;
248
249 /// analyzeCompare - For a comparison instruction, return the source registers
250 /// in SrcReg and SrcReg2 if having two register operands, and the value it
251 /// compares against in CmpValue. Return true if the comparison instruction
252 /// can be analyzed.
253 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
254 unsigned &SrcReg2, int &CmpMask,
255 int &CmpValue) const override;
256
257 /// optimizeCompareInstr - Convert the instruction to set the zero flag so
258 /// that we can remove a "comparison with zero"; Remove a redundant CMP
259 /// instruction if the flags can be updated in the same way by an earlier
260 /// instruction such as SUB.
261 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
262 unsigned SrcReg2, int CmpMask, int CmpValue,
263 const MachineRegisterInfo *MRI) const override;
264
265 bool analyzeSelect(const MachineInstr &MI,
266 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
267 unsigned &FalseOp, bool &Optimizable) const override;
268
269 MachineInstr *optimizeSelect(MachineInstr &MI,
270 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
271 bool) const override;
272
273 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
274 /// instruction, try to fold the immediate into the use instruction.
275 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
276 MachineRegisterInfo *MRI) const override;
277
278 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
279 const MachineInstr &MI) const override;
280
281 int getOperandLatency(const InstrItineraryData *ItinData,
282 const MachineInstr &DefMI, unsigned DefIdx,
283 const MachineInstr &UseMI,
284 unsigned UseIdx) const override;
285 int getOperandLatency(const InstrItineraryData *ItinData,
286 SDNode *DefNode, unsigned DefIdx,
287 SDNode *UseNode, unsigned UseIdx) const override;
288
289 /// VFP/NEON execution domains.
290 std::pair<uint16_t, uint16_t>
291 getExecutionDomain(const MachineInstr &MI) const override;
292 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
293
294 unsigned
295 getPartialRegUpdateClearance(const MachineInstr &, unsigned,
296 const TargetRegisterInfo *) const override;
297 void breakPartialRegDependency(MachineInstr &, unsigned,
298 const TargetRegisterInfo *TRI) const override;
299
300 /// Get the number of addresses by LDM or VLDM or zero for unknown.
301 unsigned getNumLDMAddresses(const MachineInstr &MI) const;
302
303 private:
304 unsigned getInstBundleLength(const MachineInstr &MI) const;
305
306 int getVLDMDefCycle(const InstrItineraryData *ItinData,
307 const MCInstrDesc &DefMCID,
308 unsigned DefClass,
309 unsigned DefIdx, unsigned DefAlign) const;
310 int getLDMDefCycle(const InstrItineraryData *ItinData,
311 const MCInstrDesc &DefMCID,
312 unsigned DefClass,
313 unsigned DefIdx, unsigned DefAlign) const;
314 int getVSTMUseCycle(const InstrItineraryData *ItinData,
315 const MCInstrDesc &UseMCID,
316 unsigned UseClass,
317 unsigned UseIdx, unsigned UseAlign) const;
318 int getSTMUseCycle(const InstrItineraryData *ItinData,
319 const MCInstrDesc &UseMCID,
320 unsigned UseClass,
321 unsigned UseIdx, unsigned UseAlign) const;
322 int getOperandLatency(const InstrItineraryData *ItinData,
323 const MCInstrDesc &DefMCID,
324 unsigned DefIdx, unsigned DefAlign,
325 const MCInstrDesc &UseMCID,
326 unsigned UseIdx, unsigned UseAlign) const;
327
328 int getOperandLatencyImpl(const InstrItineraryData *ItinData,
329 const MachineInstr &DefMI, unsigned DefIdx,
330 const MCInstrDesc &DefMCID, unsigned DefAdj,
331 const MachineOperand &DefMO, unsigned Reg,
332 const MachineInstr &UseMI, unsigned UseIdx,
333 const MCInstrDesc &UseMCID, unsigned UseAdj) const;
334
335 unsigned getPredicationCost(const MachineInstr &MI) const override;
336
337 unsigned getInstrLatency(const InstrItineraryData *ItinData,
338 const MachineInstr &MI,
339 unsigned *PredCost = nullptr) const override;
340
341 int getInstrLatency(const InstrItineraryData *ItinData,
342 SDNode *Node) const override;
343
344 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
345 const MachineRegisterInfo *MRI,
346 const MachineInstr &DefMI, unsigned DefIdx,
347 const MachineInstr &UseMI,
348 unsigned UseIdx) const override;
349 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
350 const MachineInstr &DefMI,
351 unsigned DefIdx) const override;
352
353 /// verifyInstruction - Perform target specific instruction verification.
354 bool verifyInstruction(const MachineInstr &MI,
355 StringRef &ErrInfo) const override;
356
357 virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0;
358
359 void expandMEMCPY(MachineBasicBlock::iterator) const;
360
361 private:
362 /// Modeling special VFP / NEON fp MLA / MLS hazards.
363
364 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
365 /// MLx table.
366 DenseMap<unsigned, unsigned> MLxEntryMap;
367
368 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
369 /// stalls when scheduled together with fp MLA / MLS opcodes.
370 SmallSet<unsigned, 16> MLxHazardOpcodes;
371
372 public:
373 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
374 /// instruction.
isFpMLxInstruction(unsigned Opcode)375 bool isFpMLxInstruction(unsigned Opcode) const {
376 return MLxEntryMap.count(Opcode);
377 }
378
379 /// isFpMLxInstruction - This version also returns the multiply opcode and the
380 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
381 /// the MLX instructions with an extra lane operand.
382 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
383 unsigned &AddSubOpc, bool &NegAcc,
384 bool &HasLane) const;
385
386 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
387 /// will cause stalls when scheduled after (within 4-cycle window) a fp
388 /// MLA / MLS instruction.
canCauseFpMLxStall(unsigned Opcode)389 bool canCauseFpMLxStall(unsigned Opcode) const {
390 return MLxHazardOpcodes.count(Opcode);
391 }
392
393 /// Returns true if the instruction has a shift by immediate that can be
394 /// executed in one cycle less.
395 bool isSwiftFastImmShift(const MachineInstr *MI) const;
396 };
397
398 static inline
AddDefaultPred(const MachineInstrBuilder & MIB)399 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
400 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
401 }
402
403 static inline
AddDefaultCC(const MachineInstrBuilder & MIB)404 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
405 return MIB.addReg(0);
406 }
407
408 static inline
409 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
410 bool isDead = false) {
411 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
412 }
413
414 static inline
AddNoT1CC(const MachineInstrBuilder & MIB)415 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
416 return MIB.addReg(0);
417 }
418
419 static inline
isUncondBranchOpcode(int Opc)420 bool isUncondBranchOpcode(int Opc) {
421 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
422 }
423
424 static inline
isCondBranchOpcode(int Opc)425 bool isCondBranchOpcode(int Opc) {
426 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
427 }
428
429 static inline
isJumpTableBranchOpcode(int Opc)430 bool isJumpTableBranchOpcode(int Opc) {
431 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
432 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
433 }
434
435 static inline
isIndirectBranchOpcode(int Opc)436 bool isIndirectBranchOpcode(int Opc) {
437 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
438 }
439
isPopOpcode(int Opc)440 static inline bool isPopOpcode(int Opc) {
441 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
442 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
443 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
444 }
445
isPushOpcode(int Opc)446 static inline bool isPushOpcode(int Opc) {
447 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
448 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
449 }
450
451 /// getInstrPredicate - If instruction is predicated, returns its predicate
452 /// condition, otherwise returns AL. It also returns the condition code
453 /// register by reference.
454 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
455
456 unsigned getMatchingCondBranchOpcode(unsigned Opc);
457
458 /// Determine if MI can be folded into an ARM MOVCC instruction, and return the
459 /// opcode of the SSA instruction representing the conditional MI.
460 unsigned canFoldARMInstrIntoMOVCC(unsigned Reg,
461 MachineInstr *&MI,
462 const MachineRegisterInfo &MRI);
463
464 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
465 /// the instruction is encoded with an 'S' bit is determined by the optional
466 /// CPSR def operand.
467 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
468
469 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
470 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
471 /// code.
472 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
473 MachineBasicBlock::iterator &MBBI,
474 const DebugLoc &dl, unsigned DestReg,
475 unsigned BaseReg, int NumBytes,
476 ARMCC::CondCodes Pred, unsigned PredReg,
477 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
478
479 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
480 MachineBasicBlock::iterator &MBBI,
481 const DebugLoc &dl, unsigned DestReg,
482 unsigned BaseReg, int NumBytes,
483 ARMCC::CondCodes Pred, unsigned PredReg,
484 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
485 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
486 MachineBasicBlock::iterator &MBBI,
487 const DebugLoc &dl, unsigned DestReg,
488 unsigned BaseReg, int NumBytes,
489 const TargetInstrInfo &TII,
490 const ARMBaseRegisterInfo &MRI,
491 unsigned MIFlags = 0);
492
493 /// Tries to add registers to the reglist of a given base-updating
494 /// push/pop instruction to adjust the stack by an additional
495 /// NumBytes. This can save a few bytes per function in code-size, but
496 /// obviously generates more memory traffic. As such, it only takes
497 /// effect in functions being optimised for size.
498 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
499 MachineFunction &MF, MachineInstr *MI,
500 unsigned NumBytes);
501
502 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
503 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
504 /// offset could not be handled directly in MI, and return the left-over
505 /// portion by reference.
506 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
507 unsigned FrameReg, int &Offset,
508 const ARMBaseInstrInfo &TII);
509
510 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
511 unsigned FrameReg, int &Offset,
512 const ARMBaseInstrInfo &TII);
513
514 } // End llvm namespace
515
516 #endif
517