1 //===-- MSP430InstrInfo.cpp - MSP430 Instruction Information --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MSP430 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "MSP430InstrInfo.h"
15 #include "MSP430.h"
16 #include "MSP430MachineFunctionInfo.h"
17 #include "MSP430TargetMachine.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/IR/Function.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/TargetRegistry.h"
24
25 using namespace llvm;
26
27 #define GET_INSTRINFO_CTOR_DTOR
28 #include "MSP430GenInstrInfo.inc"
29
30 // Pin the vtable to this file.
anchor()31 void MSP430InstrInfo::anchor() {}
32
MSP430InstrInfo(MSP430Subtarget & STI)33 MSP430InstrInfo::MSP430InstrInfo(MSP430Subtarget &STI)
34 : MSP430GenInstrInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
35 RI() {}
36
storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,unsigned SrcReg,bool isKill,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const37 void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
38 MachineBasicBlock::iterator MI,
39 unsigned SrcReg, bool isKill, int FrameIdx,
40 const TargetRegisterClass *RC,
41 const TargetRegisterInfo *TRI) const {
42 DebugLoc DL;
43 if (MI != MBB.end()) DL = MI->getDebugLoc();
44 MachineFunction &MF = *MBB.getParent();
45 MachineFrameInfo &MFI = *MF.getFrameInfo();
46
47 MachineMemOperand *MMO = MF.getMachineMemOperand(
48 MachinePointerInfo::getFixedStack(MF, FrameIdx),
49 MachineMemOperand::MOStore, MFI.getObjectSize(FrameIdx),
50 MFI.getObjectAlignment(FrameIdx));
51
52 if (RC == &MSP430::GR16RegClass)
53 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
54 .addFrameIndex(FrameIdx).addImm(0)
55 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
56 else if (RC == &MSP430::GR8RegClass)
57 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
58 .addFrameIndex(FrameIdx).addImm(0)
59 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
60 else
61 llvm_unreachable("Cannot store this register to stack slot!");
62 }
63
loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,unsigned DestReg,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const64 void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
65 MachineBasicBlock::iterator MI,
66 unsigned DestReg, int FrameIdx,
67 const TargetRegisterClass *RC,
68 const TargetRegisterInfo *TRI) const{
69 DebugLoc DL;
70 if (MI != MBB.end()) DL = MI->getDebugLoc();
71 MachineFunction &MF = *MBB.getParent();
72 MachineFrameInfo &MFI = *MF.getFrameInfo();
73
74 MachineMemOperand *MMO = MF.getMachineMemOperand(
75 MachinePointerInfo::getFixedStack(MF, FrameIdx),
76 MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIdx),
77 MFI.getObjectAlignment(FrameIdx));
78
79 if (RC == &MSP430::GR16RegClass)
80 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
81 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx)
82 .addImm(0).addMemOperand(MMO);
83 else if (RC == &MSP430::GR8RegClass)
84 BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
85 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx)
86 .addImm(0).addMemOperand(MMO);
87 else
88 llvm_unreachable("Cannot store this register to stack slot!");
89 }
90
copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,unsigned DestReg,unsigned SrcReg,bool KillSrc) const91 void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator I,
93 const DebugLoc &DL, unsigned DestReg,
94 unsigned SrcReg, bool KillSrc) const {
95 unsigned Opc;
96 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
97 Opc = MSP430::MOV16rr;
98 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
99 Opc = MSP430::MOV8rr;
100 else
101 llvm_unreachable("Impossible reg-to-reg copy");
102
103 BuildMI(MBB, I, DL, get(Opc), DestReg)
104 .addReg(SrcReg, getKillRegState(KillSrc));
105 }
106
RemoveBranch(MachineBasicBlock & MBB) const107 unsigned MSP430InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
108 MachineBasicBlock::iterator I = MBB.end();
109 unsigned Count = 0;
110
111 while (I != MBB.begin()) {
112 --I;
113 if (I->isDebugValue())
114 continue;
115 if (I->getOpcode() != MSP430::JMP &&
116 I->getOpcode() != MSP430::JCC &&
117 I->getOpcode() != MSP430::Br &&
118 I->getOpcode() != MSP430::Bm)
119 break;
120 // Remove the branch.
121 I->eraseFromParent();
122 I = MBB.end();
123 ++Count;
124 }
125
126 return Count;
127 }
128
129 bool MSP430InstrInfo::
ReverseBranchCondition(SmallVectorImpl<MachineOperand> & Cond) const130 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
131 assert(Cond.size() == 1 && "Invalid Xbranch condition!");
132
133 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
134
135 switch (CC) {
136 default: llvm_unreachable("Invalid branch condition!");
137 case MSP430CC::COND_E:
138 CC = MSP430CC::COND_NE;
139 break;
140 case MSP430CC::COND_NE:
141 CC = MSP430CC::COND_E;
142 break;
143 case MSP430CC::COND_L:
144 CC = MSP430CC::COND_GE;
145 break;
146 case MSP430CC::COND_GE:
147 CC = MSP430CC::COND_L;
148 break;
149 case MSP430CC::COND_HS:
150 CC = MSP430CC::COND_LO;
151 break;
152 case MSP430CC::COND_LO:
153 CC = MSP430CC::COND_HS;
154 break;
155 }
156
157 Cond[0].setImm(CC);
158 return false;
159 }
160
isUnpredicatedTerminator(const MachineInstr & MI) const161 bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
162 if (!MI.isTerminator())
163 return false;
164
165 // Conditional branch is a special case.
166 if (MI.isBranch() && !MI.isBarrier())
167 return true;
168 if (!MI.isPredicable())
169 return true;
170 return !isPredicated(MI);
171 }
172
analyzeBranch(MachineBasicBlock & MBB,MachineBasicBlock * & TBB,MachineBasicBlock * & FBB,SmallVectorImpl<MachineOperand> & Cond,bool AllowModify) const173 bool MSP430InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
174 MachineBasicBlock *&TBB,
175 MachineBasicBlock *&FBB,
176 SmallVectorImpl<MachineOperand> &Cond,
177 bool AllowModify) const {
178 // Start from the bottom of the block and work up, examining the
179 // terminator instructions.
180 MachineBasicBlock::iterator I = MBB.end();
181 while (I != MBB.begin()) {
182 --I;
183 if (I->isDebugValue())
184 continue;
185
186 // Working from the bottom, when we see a non-terminator
187 // instruction, we're done.
188 if (!isUnpredicatedTerminator(*I))
189 break;
190
191 // A terminator that isn't a branch can't easily be handled
192 // by this analysis.
193 if (!I->isBranch())
194 return true;
195
196 // Cannot handle indirect branches.
197 if (I->getOpcode() == MSP430::Br ||
198 I->getOpcode() == MSP430::Bm)
199 return true;
200
201 // Handle unconditional branches.
202 if (I->getOpcode() == MSP430::JMP) {
203 if (!AllowModify) {
204 TBB = I->getOperand(0).getMBB();
205 continue;
206 }
207
208 // If the block has any instructions after a JMP, delete them.
209 while (std::next(I) != MBB.end())
210 std::next(I)->eraseFromParent();
211 Cond.clear();
212 FBB = nullptr;
213
214 // Delete the JMP if it's equivalent to a fall-through.
215 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
216 TBB = nullptr;
217 I->eraseFromParent();
218 I = MBB.end();
219 continue;
220 }
221
222 // TBB is used to indicate the unconditinal destination.
223 TBB = I->getOperand(0).getMBB();
224 continue;
225 }
226
227 // Handle conditional branches.
228 assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");
229 MSP430CC::CondCodes BranchCode =
230 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
231 if (BranchCode == MSP430CC::COND_INVALID)
232 return true; // Can't handle weird stuff.
233
234 // Working from the bottom, handle the first conditional branch.
235 if (Cond.empty()) {
236 FBB = TBB;
237 TBB = I->getOperand(0).getMBB();
238 Cond.push_back(MachineOperand::CreateImm(BranchCode));
239 continue;
240 }
241
242 // Handle subsequent conditional branches. Only handle the case where all
243 // conditional branches branch to the same destination.
244 assert(Cond.size() == 1);
245 assert(TBB);
246
247 // Only handle the case where all conditional branches branch to
248 // the same destination.
249 if (TBB != I->getOperand(0).getMBB())
250 return true;
251
252 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
253 // If the conditions are the same, we can leave them alone.
254 if (OldBranchCode == BranchCode)
255 continue;
256
257 return true;
258 }
259
260 return false;
261 }
262
InsertBranch(MachineBasicBlock & MBB,MachineBasicBlock * TBB,MachineBasicBlock * FBB,ArrayRef<MachineOperand> Cond,const DebugLoc & DL) const263 unsigned MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB,
264 MachineBasicBlock *TBB,
265 MachineBasicBlock *FBB,
266 ArrayRef<MachineOperand> Cond,
267 const DebugLoc &DL) const {
268 // Shouldn't be a fall through.
269 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
270 assert((Cond.size() == 1 || Cond.size() == 0) &&
271 "MSP430 branch conditions have one component!");
272
273 if (Cond.empty()) {
274 // Unconditional branch?
275 assert(!FBB && "Unconditional branch with multiple successors!");
276 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
277 return 1;
278 }
279
280 // Conditional branch.
281 unsigned Count = 0;
282 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
283 ++Count;
284
285 if (FBB) {
286 // Two-way Conditional branch. Insert the second branch.
287 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
288 ++Count;
289 }
290 return Count;
291 }
292
293 /// GetInstSize - Return the number of bytes of code the specified
294 /// instruction may be. This returns the maximum number of bytes.
295 ///
GetInstSizeInBytes(const MachineInstr & MI) const296 unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const {
297 const MCInstrDesc &Desc = MI.getDesc();
298
299 switch (Desc.TSFlags & MSP430II::SizeMask) {
300 default:
301 switch (Desc.getOpcode()) {
302 default: llvm_unreachable("Unknown instruction size!");
303 case TargetOpcode::CFI_INSTRUCTION:
304 case TargetOpcode::EH_LABEL:
305 case TargetOpcode::IMPLICIT_DEF:
306 case TargetOpcode::KILL:
307 case TargetOpcode::DBG_VALUE:
308 return 0;
309 case TargetOpcode::INLINEASM: {
310 const MachineFunction *MF = MI.getParent()->getParent();
311 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
312 return TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
313 *MF->getTarget().getMCAsmInfo());
314 }
315 }
316 case MSP430II::SizeSpecial:
317 switch (MI.getOpcode()) {
318 default: llvm_unreachable("Unknown instruction size!");
319 case MSP430::SAR8r1c:
320 case MSP430::SAR16r1c:
321 return 4;
322 }
323 case MSP430II::Size2Bytes:
324 return 2;
325 case MSP430II::Size4Bytes:
326 return 4;
327 case MSP430II::Size6Bytes:
328 return 6;
329 }
330 }
331