1//===-- MipsCondMov.td - Describe Mips Conditional Moves --*- tablegen -*--===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This is the Conditional Moves implementation. 11// 12//===----------------------------------------------------------------------===// 13 14// Conditional moves: 15// These instructions are expanded in 16// MipsISelLowering::EmitInstrWithCustomInserter if target does not have 17// conditional move instructions. 18// cond:int, data:int 19class CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC, 20 InstrItinClass Itin> : 21 InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F), 22 !strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR, opstr> { 23 let Constraints = "$F = $rd"; 24} 25 26// cond:int, data:float 27class CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC, 28 InstrItinClass Itin> : 29 InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F), 30 !strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR, opstr>, 31 HARDFLOAT { 32 let Constraints = "$F = $fd"; 33} 34 35// cond:float, data:int 36class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 37 SDPatternOperator OpNode = null_frag> : 38 InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F), 39 !strconcat(opstr, "\t$rd, $rs, $fcc"), 40 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))], 41 Itin, FrmFR, opstr>, HARDFLOAT { 42 let Constraints = "$F = $rd"; 43} 44 45// cond:float, data:float 46class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 47 SDPatternOperator OpNode = null_frag> : 48 InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F), 49 !strconcat(opstr, "\t$fd, $fs, $fcc"), 50 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))], 51 Itin, FrmFR, opstr>, HARDFLOAT { 52 let Constraints = "$F = $fd"; 53} 54 55// select patterns 56multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC, 57 Instruction MOVZInst, Instruction SLTOp, 58 Instruction SLTuOp, Instruction SLTiOp, 59 Instruction SLTiuOp> { 60 def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 61 (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>; 62 def : MipsPat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 63 (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>; 64 def : MipsPat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F), 65 (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>; 66 def : MipsPat<(select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F), 67 (MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>; 68 def : MipsPat<(select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 69 (MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>; 70 def : MipsPat<(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 71 (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>; 72 def : MipsPat<(select (i32 (setgt CRC:$lhs, immSExt16Plus1:$rhs)), 73 DRC:$T, DRC:$F), 74 (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, (Plus1 imm:$rhs)), DRC:$F)>; 75 def : MipsPat<(select (i32 (setugt CRC:$lhs, immSExt16Plus1:$rhs)), 76 DRC:$T, DRC:$F), 77 (MOVZInst DRC:$T, (SLTiuOp CRC:$lhs, (Plus1 imm:$rhs)), 78 DRC:$F)>; 79} 80 81multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC, 82 Instruction MOVZInst, Instruction XOROp> { 83 def : MipsPat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 84 (MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>; 85 def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F), 86 (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>; 87} 88 89multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC, 90 Instruction MOVZInst, Instruction XORiOp> { 91 def : MipsPat< 92 (select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F), 93 (MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>; 94} 95 96multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst, 97 Instruction XOROp> { 98 def : MipsPat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 99 (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>; 100 def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F), 101 (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>; 102 def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F), 103 (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>; 104} 105 106// Instantiation of instructions. 107def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, II_MOVZ>, 108 ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6; 109 110let isCodeGenOnly = 1 in { 111 def MOVZ_I_I64 : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd, II_MOVZ>, 112 ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6; 113 def MOVZ_I64_I : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd, II_MOVZ>, 114 ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6; 115 def MOVZ_I64_I64 : CMov_I_I_FT<"movz", GPR64Opnd, GPR64Opnd, II_MOVZ>, 116 ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6; 117} 118 119def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, II_MOVN>, 120 ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; 121 122let isCodeGenOnly = 1 in { 123 def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, II_MOVN>, 124 ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; 125 def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, II_MOVN>, 126 ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; 127 def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, II_MOVN>, 128 ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6; 129} 130 131def MOVZ_I_S : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, II_MOVZ_S>, 132 CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6; 133 134let isCodeGenOnly = 1 in 135def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, II_MOVZ_S>, 136 CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 137 138def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>, 139 CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6; 140 141let isCodeGenOnly = 1 in 142def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>, 143 CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 144 145def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd, 146 II_MOVZ_D>, CMov_I_F_FM<18, 17>, 147 INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; 148def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd, 149 II_MOVN_D>, CMov_I_F_FM<19, 17>, 150 INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; 151 152let DecoderNamespace = "Mips64" in { 153 def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>, 154 CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; 155 def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>, 156 CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; 157 let isCodeGenOnly = 1 in { 158 def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd, II_MOVZ_D>, 159 CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; 160 def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd, II_MOVN_D>, 161 CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; 162 } 163} 164 165def MOVT_I : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>, 166 CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6; 167 168let isCodeGenOnly = 1 in 169def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, II_MOVT, MipsCMovFP_T>, 170 CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 171 172def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>, 173 CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6; 174 175let isCodeGenOnly = 1 in 176def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>, 177 CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 178 179def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>, 180 CMov_F_F_FM<16, 1>, INSN_MIPS4_32_NOT_32R6_64R6; 181def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>, 182 CMov_F_F_FM<16, 0>, INSN_MIPS4_32_NOT_32R6_64R6; 183 184def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D, 185 MipsCMovFP_T>, CMov_F_F_FM<17, 1>, 186 INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; 187def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D, 188 MipsCMovFP_F>, CMov_F_F_FM<17, 0>, 189 INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; 190 191let DecoderNamespace = "Mips64" in { 192 def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>, 193 CMov_F_F_FM<17, 1>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; 194 def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>, 195 CMov_F_F_FM<17, 0>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; 196} 197 198// Instantiation of conditional move patterns. 199defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>, 200 INSN_MIPS4_32_NOT_32R6_64R6; 201defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6; 202defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi>, INSN_MIPS4_32_NOT_32R6_64R6; 203 204defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>, 205 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 206defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64, SLTiu64>, 207 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 208defm : MovzPats0<GPR64, GPR64, MOVZ_I_I64, SLT64, SLTu64, SLTi64, SLTiu64>, 209 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 210defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>, 211 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 212defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>, 213 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 214defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64>, 215 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 216defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>, 217 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 218defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>, 219 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 220defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64>, 221 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 222 223defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6; 224 225defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6, 226 GPR_64; 227defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6, 228 GPR_64; 229defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6, 230 GPR_64; 231 232defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>, 233 INSN_MIPS4_32_NOT_32R6_64R6; 234defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6; 235defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6; 236 237defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64, SLTiu64>, 238 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64; 239defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6, 240 GPR_64; 241defm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6, 242 GPR_64; 243 244defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>, 245 INSN_MIPS4_32_NOT_32R6_64R6, FGR_32; 246defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6, 247 FGR_32; 248defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6, 249 FGR_32; 250 251defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>, 252 INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; 253defm : MovzPats0<GPR64, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64, SLTiu64>, 254 INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; 255defm : MovzPats1<GPR32, FGR64, MOVZ_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6, 256 FGR_64; 257defm : MovzPats1<GPR64, FGR64, MOVZ_I64_D64, XOR64>, 258 INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; 259defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6, 260 FGR_64; 261defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6, 262 FGR_64; 263 264// For targets that don't have conditional-move instructions 265// we have to match SELECT nodes with pseudo instructions. 266let usesCustomInserter = 1 in { 267 class Select_Pseudo<RegisterOperand RC> : 268 PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F), 269 [(set RC:$dst, (select GPR32Opnd:$cond, RC:$T, RC:$F))]>, 270 ISA_MIPS1_NOT_4_32; 271 272 class SelectFP_Pseudo_T<RegisterOperand RC> : 273 PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F), 274 [(set RC:$dst, (MipsCMovFP_T RC:$T, GPR32Opnd:$cond, RC:$F))]>, 275 ISA_MIPS1_NOT_4_32; 276 277 class SelectFP_Pseudo_F<RegisterOperand RC> : 278 PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F), 279 [(set RC:$dst, (MipsCMovFP_F RC:$T, GPR32Opnd:$cond, RC:$F))]>, 280 ISA_MIPS1_NOT_4_32; 281} 282 283def PseudoSELECT_I : Select_Pseudo<GPR32Opnd>; 284def PseudoSELECT_I64 : Select_Pseudo<GPR64Opnd>; 285def PseudoSELECT_S : Select_Pseudo<FGR32Opnd>; 286def PseudoSELECT_D32 : Select_Pseudo<AFGR64Opnd>, FGR_32; 287def PseudoSELECT_D64 : Select_Pseudo<FGR64Opnd>, FGR_64; 288 289def PseudoSELECTFP_T_I : SelectFP_Pseudo_T<GPR32Opnd>; 290def PseudoSELECTFP_T_I64 : SelectFP_Pseudo_T<GPR64Opnd>; 291def PseudoSELECTFP_T_S : SelectFP_Pseudo_T<FGR32Opnd>; 292def PseudoSELECTFP_T_D32 : SelectFP_Pseudo_T<AFGR64Opnd>, FGR_32; 293def PseudoSELECTFP_T_D64 : SelectFP_Pseudo_T<FGR64Opnd>, FGR_64; 294 295def PseudoSELECTFP_F_I : SelectFP_Pseudo_F<GPR32Opnd>; 296def PseudoSELECTFP_F_I64 : SelectFP_Pseudo_F<GPR64Opnd>; 297def PseudoSELECTFP_F_S : SelectFP_Pseudo_F<FGR32Opnd>; 298def PseudoSELECTFP_F_D32 : SelectFP_Pseudo_F<AFGR64Opnd>, FGR_32; 299def PseudoSELECTFP_F_D64 : SelectFP_Pseudo_F<FGR64Opnd>, FGR_64; 300