1; Check VMX 128-bit integer operations 2; 3; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s 4; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s 5 6define <1 x i128> @test_add(<1 x i128> %x, <1 x i128> %y) nounwind { 7 %result = add <1 x i128> %x, %y 8 ret <1 x i128> %result 9; CHECK-LABEL: @test_add 10; CHECK: vadduqm 2, 2, 3 11} 12 13define <1 x i128> @increment_by_one(<1 x i128> %x) nounwind { 14 %result = add <1 x i128> %x, <i128 1> 15 ret <1 x i128> %result 16; CHECK-LABEL: @increment_by_one 17; CHECK: vadduqm 2, 2, 3 18} 19 20define <1 x i128> @increment_by_val(<1 x i128> %x, i128 %val) nounwind { 21 %tmpvec = insertelement <1 x i128> <i128 0>, i128 %val, i32 0 22 %tmpvec2 = insertelement <1 x i128> %tmpvec, i128 %val, i32 1 23 %result = add <1 x i128> %x, %tmpvec2 24 ret <1 x i128> %result 25; CHECK-LABEL: @increment_by_val 26; CHECK: vadduqm 2, 2, 3 27} 28 29define <1 x i128> @test_sub(<1 x i128> %x, <1 x i128> %y) nounwind { 30 %result = sub <1 x i128> %x, %y 31 ret <1 x i128> %result 32; CHECK-LABEL: @test_sub 33; CHECK: vsubuqm 2, 2, 3 34} 35 36define <1 x i128> @decrement_by_one(<1 x i128> %x) nounwind { 37 %result = sub <1 x i128> %x, <i128 1> 38 ret <1 x i128> %result 39; CHECK-LABEL: @decrement_by_one 40; CHECK: vsubuqm 2, 2, 3 41} 42 43define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind { 44 %tmpvec = insertelement <1 x i128> <i128 0>, i128 %val, i32 0 45 %tmpvec2 = insertelement <1 x i128> %tmpvec, i128 %val, i32 1 46 %result = sub <1 x i128> %x, %tmpvec2 47 ret <1 x i128> %result 48; CHECK-LABEL: @decrement_by_val 49; CHECK: vsubuqm 2, 2, 3 50} 51 52declare <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x, 53 <1 x i128> %y, 54 <1 x i128> %z) nounwind readnone 55declare <1 x i128> @llvm.ppc.altivec.vaddcuq(<1 x i128> %x, 56 <1 x i128> %y) nounwind readnone 57declare <1 x i128> @llvm.ppc.altivec.vaddecuq(<1 x i128> %x, 58 <1 x i128> %y, 59 <1 x i128> %z) nounwind readnone 60declare <1 x i128> @llvm.ppc.altivec.vsubeuqm(<1 x i128> %x, 61 <1 x i128> %y, 62 <1 x i128> %z) nounwind readnone 63declare <1 x i128> @llvm.ppc.altivec.vsubcuq(<1 x i128> %x, 64 <1 x i128> %y) nounwind readnone 65declare <1 x i128> @llvm.ppc.altivec.vsubecuq(<1 x i128> %x, 66 <1 x i128> %y, 67 <1 x i128> %z) nounwind readnone 68 69define <1 x i128> @test_vaddeuqm(<1 x i128> %x, 70 <1 x i128> %y, 71 <1 x i128> %z) nounwind { 72 %tmp = tail call <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x, 73 <1 x i128> %y, 74 <1 x i128> %z) 75 ret <1 x i128> %tmp 76; CHECK-LABEL: @test_vaddeuqm 77; CHECK: vaddeuqm 2, 2, 3, 4 78} 79 80define <1 x i128> @test_vaddcuq(<1 x i128> %x, 81 <1 x i128> %y) nounwind { 82 %tmp = tail call <1 x i128> @llvm.ppc.altivec.vaddcuq(<1 x i128> %x, 83 <1 x i128> %y) 84 ret <1 x i128> %tmp 85; CHECK-LABEL: @test_vaddcuq 86; CHECK: vaddcuq 2, 2, 3 87} 88 89define <1 x i128> @test_vaddecuq(<1 x i128> %x, 90 <1 x i128> %y, 91 <1 x i128> %z) nounwind { 92 %tmp = tail call <1 x i128> @llvm.ppc.altivec.vaddecuq(<1 x i128> %x, 93 <1 x i128> %y, 94 <1 x i128> %z) 95 ret <1 x i128> %tmp 96; CHECK-LABEL: @test_vaddecuq 97; CHECK: vaddecuq 2, 2, 3, 4 98} 99 100define <1 x i128> @test_vsubeuqm(<1 x i128> %x, 101 <1 x i128> %y, 102 <1 x i128> %z) nounwind { 103 %tmp = tail call <1 x i128> @llvm.ppc.altivec.vsubeuqm(<1 x i128> %x, 104 <1 x i128> %y, 105 <1 x i128> %z) 106 ret <1 x i128> %tmp 107; CHECK-LABEL: test_vsubeuqm 108; CHECK: vsubeuqm 2, 2, 3, 4 109} 110 111define <1 x i128> @test_vsubcuq(<1 x i128> %x, 112 <1 x i128> %y) nounwind { 113 %tmp = tail call <1 x i128> @llvm.ppc.altivec.vsubcuq(<1 x i128> %x, 114 <1 x i128> %y) 115 ret <1 x i128> %tmp 116; CHECK-LABEL: test_vsubcuq 117; CHECK: vsubcuq 2, 2, 3 118} 119 120define <1 x i128> @test_vsubecuq(<1 x i128> %x, 121 <1 x i128> %y, 122 <1 x i128> %z) nounwind { 123 %tmp = tail call <1 x i128> @llvm.ppc.altivec.vsubecuq(<1 x i128> %x, 124 <1 x i128> %y, 125 <1 x i128> %z) 126 ret <1 x i128> %tmp 127; CHECK-LABEL: test_vsubecuq 128; CHECK: vsubecuq 2, 2, 3, 4 129} 130 131