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1 /*
2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * on the rights to use, copy, modify, merge, publish, distribute, sub
8  * license, and/or sell copies of the Software, and to permit persons to whom
9  * the Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
22  */
23 #include "r600_pipe.h"
24 #include "r600_public.h"
25 #include "r600_isa.h"
26 #include "evergreen_compute.h"
27 #include "r600d.h"
28 
29 #include "sb/sb_public.h"
30 
31 #include <errno.h>
32 #include "pipe/p_shader_tokens.h"
33 #include "util/u_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_screen.h"
36 #include "util/u_simple_shaders.h"
37 #include "util/u_upload_mgr.h"
38 #include "util/u_math.h"
39 #include "vl/vl_decoder.h"
40 #include "vl/vl_video_buffer.h"
41 #include "radeon_video.h"
42 #include "radeon_uvd.h"
43 #include "util/os_time.h"
44 
45 static const struct debug_named_value r600_debug_options[] = {
46 	/* features */
47 	{ "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
48 
49 	/* shader backend */
50 	{ "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
51 	{ "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
52 	{ "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
53 	{ "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
54 	{ "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
55 	{ "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
56 	{ "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
57 	{ "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
58 
59 	DEBUG_NAMED_VALUE_END /* must be last */
60 };
61 
62 /*
63  * pipe_context
64  */
65 
r600_destroy_context(struct pipe_context * context)66 static void r600_destroy_context(struct pipe_context *context)
67 {
68 	struct r600_context *rctx = (struct r600_context *)context;
69 	unsigned sh, i;
70 
71 	r600_isa_destroy(rctx->isa);
72 
73 	r600_sb_context_destroy(rctx->sb_context);
74 
75 	for (sh = 0; sh < (rctx->b.chip_class < EVERGREEN ? R600_NUM_HW_STAGES : EG_NUM_HW_STAGES); sh++) {
76 		r600_resource_reference(&rctx->scratch_buffers[sh].buffer, NULL);
77 	}
78 	r600_resource_reference(&rctx->dummy_cmask, NULL);
79 	r600_resource_reference(&rctx->dummy_fmask, NULL);
80 
81 	if (rctx->append_fence)
82 		pipe_resource_reference((struct pipe_resource**)&rctx->append_fence, NULL);
83 	for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
84 		rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, NULL);
85 		free(rctx->driver_consts[sh].constants);
86 	}
87 
88 	if (rctx->fixed_func_tcs_shader)
89 		rctx->b.b.delete_tcs_state(&rctx->b.b, rctx->fixed_func_tcs_shader);
90 
91 	if (rctx->dummy_pixel_shader) {
92 		rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
93 	}
94 	if (rctx->custom_dsa_flush) {
95 		rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
96 	}
97 	if (rctx->custom_blend_resolve) {
98 		rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
99 	}
100 	if (rctx->custom_blend_decompress) {
101 		rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
102 	}
103 	if (rctx->custom_blend_fastclear) {
104 		rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
105 	}
106 	util_unreference_framebuffer_state(&rctx->framebuffer.state);
107 
108 	if (rctx->gs_rings.gsvs_ring.buffer)
109 		pipe_resource_reference(&rctx->gs_rings.gsvs_ring.buffer, NULL);
110 
111 	if (rctx->gs_rings.esgs_ring.buffer)
112 		pipe_resource_reference(&rctx->gs_rings.esgs_ring.buffer, NULL);
113 
114 	for (sh = 0; sh < PIPE_SHADER_TYPES; ++sh)
115 		for (i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; ++i)
116 			rctx->b.b.set_constant_buffer(context, sh, i, NULL);
117 
118 	if (rctx->blitter) {
119 		util_blitter_destroy(rctx->blitter);
120 	}
121 	if (rctx->allocator_fetch_shader) {
122 		u_suballocator_destroy(rctx->allocator_fetch_shader);
123 	}
124 
125 	r600_release_command_buffer(&rctx->start_cs_cmd);
126 
127 	FREE(rctx->start_compute_cs_cmd.buf);
128 
129 	r600_common_context_cleanup(&rctx->b);
130 
131 	r600_resource_reference(&rctx->trace_buf, NULL);
132 	r600_resource_reference(&rctx->last_trace_buf, NULL);
133 	radeon_clear_saved_cs(&rctx->last_gfx);
134 
135 	FREE(rctx);
136 }
137 
r600_create_context(struct pipe_screen * screen,void * priv,unsigned flags)138 static struct pipe_context *r600_create_context(struct pipe_screen *screen,
139                                                 void *priv, unsigned flags)
140 {
141 	struct r600_context *rctx = CALLOC_STRUCT(r600_context);
142 	struct r600_screen* rscreen = (struct r600_screen *)screen;
143 	struct radeon_winsys *ws = rscreen->b.ws;
144 
145 	if (!rctx)
146 		return NULL;
147 
148 	rctx->b.b.screen = screen;
149 	assert(!priv);
150 	rctx->b.b.priv = NULL; /* for threaded_context_unwrap_sync */
151 	rctx->b.b.destroy = r600_destroy_context;
152 	rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
153 
154 	if (!r600_common_context_init(&rctx->b, &rscreen->b, flags))
155 		goto fail;
156 
157 	rctx->screen = rscreen;
158 	list_inithead(&rctx->texture_buffers);
159 
160 	r600_init_blit_functions(rctx);
161 
162 	if (rscreen->b.info.has_hw_decode) {
163 		rctx->b.b.create_video_codec = r600_uvd_create_decoder;
164 		rctx->b.b.create_video_buffer = r600_video_buffer_create;
165 	} else {
166 		rctx->b.b.create_video_codec = vl_create_decoder;
167 		rctx->b.b.create_video_buffer = vl_video_buffer_create;
168 	}
169 
170 	if (getenv("R600_TRACE"))
171 		rctx->is_debug = true;
172 	r600_init_common_state_functions(rctx);
173 
174 	switch (rctx->b.chip_class) {
175 	case R600:
176 	case R700:
177 		r600_init_state_functions(rctx);
178 		r600_init_atom_start_cs(rctx);
179 		rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
180 		rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
181 								      : r600_create_resolve_blend(rctx);
182 		rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
183 		rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
184 					   rctx->b.family == CHIP_RV620 ||
185 					   rctx->b.family == CHIP_RS780 ||
186 					   rctx->b.family == CHIP_RS880 ||
187 					   rctx->b.family == CHIP_RV710);
188 		break;
189 	case EVERGREEN:
190 	case CAYMAN:
191 		evergreen_init_state_functions(rctx);
192 		evergreen_init_atom_start_cs(rctx);
193 		evergreen_init_atom_start_compute_cs(rctx);
194 		rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
195 		rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
196 		rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
197 		rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
198 		rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
199 					   rctx->b.family == CHIP_PALM ||
200 					   rctx->b.family == CHIP_SUMO ||
201 					   rctx->b.family == CHIP_SUMO2 ||
202 					   rctx->b.family == CHIP_CAICOS ||
203 					   rctx->b.family == CHIP_CAYMAN ||
204 					   rctx->b.family == CHIP_ARUBA);
205 
206 		rctx->append_fence = pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
207 							 PIPE_USAGE_DEFAULT, 32);
208 		break;
209 	default:
210 		R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
211 		goto fail;
212 	}
213 
214 	rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
215 				       r600_context_gfx_flush, rctx, false);
216 	rctx->b.gfx.flush = r600_context_gfx_flush;
217 
218 	rctx->allocator_fetch_shader =
219 		u_suballocator_create(&rctx->b.b, 64 * 1024,
220 				      0, PIPE_USAGE_DEFAULT, 0, FALSE);
221 	if (!rctx->allocator_fetch_shader)
222 		goto fail;
223 
224 	rctx->isa = calloc(1, sizeof(struct r600_isa));
225 	if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
226 		goto fail;
227 
228 	if (rscreen->b.debug_flags & DBG_FORCE_DMA)
229 		rctx->b.b.resource_copy_region = rctx->b.dma_copy;
230 
231 	rctx->blitter = util_blitter_create(&rctx->b.b);
232 	if (rctx->blitter == NULL)
233 		goto fail;
234 	util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
235 	rctx->blitter->draw_rectangle = r600_draw_rectangle;
236 
237 	r600_begin_new_cs(rctx);
238 
239 	rctx->dummy_pixel_shader =
240 		util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
241 						     TGSI_SEMANTIC_GENERIC,
242 						     TGSI_INTERPOLATE_CONSTANT);
243 	rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
244 
245 	return &rctx->b.b;
246 
247 fail:
248 	r600_destroy_context(&rctx->b.b);
249 	return NULL;
250 }
251 
is_nir_enabled(struct r600_common_screen * screen)252 static bool is_nir_enabled(struct r600_common_screen *screen) {
253    return (screen->debug_flags & DBG_NIR &&
254        screen->family >= CHIP_CEDAR &&
255        screen->family < CHIP_CAYMAN);
256 }
257 
258 /*
259  * pipe_screen
260  */
261 
r600_get_param(struct pipe_screen * pscreen,enum pipe_cap param)262 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
263 {
264 	struct r600_screen *rscreen = (struct r600_screen *)pscreen;
265 	enum radeon_family family = rscreen->b.family;
266 
267 	switch (param) {
268 	/* Supported features (boolean caps). */
269 	case PIPE_CAP_NPOT_TEXTURES:
270 	case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
271 	case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
272 	case PIPE_CAP_ANISOTROPIC_FILTER:
273 	case PIPE_CAP_POINT_SPRITE:
274 	case PIPE_CAP_OCCLUSION_QUERY:
275 	case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
276 	case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
277 	case PIPE_CAP_BLEND_EQUATION_SEPARATE:
278 	case PIPE_CAP_TEXTURE_SWIZZLE:
279 	case PIPE_CAP_DEPTH_CLIP_DISABLE:
280 	case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
281 	case PIPE_CAP_SHADER_STENCIL_EXPORT:
282 	case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
283 	case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
284 	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
285 	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
286 	case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
287 	case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
288 	case PIPE_CAP_VERTEX_SHADER_SATURATE:
289 	case PIPE_CAP_SEAMLESS_CUBE_MAP:
290 	case PIPE_CAP_PRIMITIVE_RESTART:
291 	case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
292 	case PIPE_CAP_CONDITIONAL_RENDER:
293 	case PIPE_CAP_TEXTURE_BARRIER:
294 	case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
295 	case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
296 	case PIPE_CAP_TGSI_INSTANCEID:
297 	case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
298 	case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
299 	case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
300 	case PIPE_CAP_START_INSTANCE:
301 	case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
302 	case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
303 	case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
304 	case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
305 	case PIPE_CAP_TEXTURE_MULTISAMPLE:
306 	case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
307 	case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
308 	case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
309 	case PIPE_CAP_SAMPLE_SHADING:
310 	case PIPE_CAP_CLIP_HALFZ:
311 	case PIPE_CAP_POLYGON_OFFSET_CLAMP:
312 	case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
313 	case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
314 	case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
315 	case PIPE_CAP_TGSI_TXQS:
316 	case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
317 	case PIPE_CAP_INVALIDATE_BUFFER:
318 	case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
319 	case PIPE_CAP_QUERY_MEMORY_INFO:
320 	case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
321 	case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
322 	case PIPE_CAP_CLEAR_TEXTURE:
323 	case PIPE_CAP_TGSI_MUL_ZERO_WINS:
324 	case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
325 	case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
326 	case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
327         case PIPE_CAP_NIR_ATOMICS_AS_DEREF:
328 		return 1;
329 
330 	case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
331 		/* Optimal number for good TexSubImage performance on Polaris10. */
332 		return 64 * 1024 * 1024;
333 
334 	case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
335 		return rscreen->b.info.drm_minor >= 43;
336 
337 	case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
338 		return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
339 
340 	case PIPE_CAP_COMPUTE:
341 		return rscreen->b.chip_class > R700;
342 
343 	case PIPE_CAP_TGSI_TEXCOORD:
344 		return 1;
345 
346 	case PIPE_CAP_NIR_IMAGES_AS_DEREF:
347 	case PIPE_CAP_FAKE_SW_MSAA:
348 		return 0;
349 
350 	case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
351 		return MIN2(rscreen->b.info.max_alloc_size, INT_MAX);
352 
353         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
354                 return R600_MAP_BUFFER_ALIGNMENT;
355 
356 	case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
357 		return 256;
358 
359 	case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
360 		return 1;
361 
362 	case PIPE_CAP_GLSL_FEATURE_LEVEL:
363 		if (family >= CHIP_CEDAR)
364 		   return 430;
365 		/* pre-evergreen geom shaders need newer kernel */
366 		if (rscreen->b.info.drm_minor >= 37)
367 		   return 330;
368 		return 140;
369 
370 	case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
371 		return 140;
372 
373 	/* Supported except the original R600. */
374 	case PIPE_CAP_INDEP_BLEND_ENABLE:
375 	case PIPE_CAP_INDEP_BLEND_FUNC:
376 		/* R600 doesn't support per-MRT blends */
377 		return family == CHIP_R600 ? 0 : 1;
378 
379 	/* Supported on Evergreen. */
380 	case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
381 	case PIPE_CAP_CUBE_MAP_ARRAY:
382 	case PIPE_CAP_TEXTURE_GATHER_SM5:
383 	case PIPE_CAP_TEXTURE_QUERY_LOD:
384 	case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
385 	case PIPE_CAP_SAMPLER_VIEW_TARGET:
386 	case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
387 	case PIPE_CAP_TGSI_CLOCK:
388 	case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
389 	case PIPE_CAP_QUERY_BUFFER_OBJECT:
390 		return family >= CHIP_CEDAR ? 1 : 0;
391 	case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
392 		return family >= CHIP_CEDAR ? 4 : 0;
393 	case PIPE_CAP_DRAW_INDIRECT:
394 		/* kernel command checker support is also required */
395 		return family >= CHIP_CEDAR && rscreen->b.info.drm_minor >= 41;
396 
397 	case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
398 		return family >= CHIP_CEDAR ? 0 : 1;
399 
400 	case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
401 		return 8;
402 
403 	case PIPE_CAP_MAX_GS_INVOCATIONS:
404 		return 32;
405 
406 	/* shader buffer objects */
407 	case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
408 		return 1 << 27;
409 	case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
410 		return 8;
411 
412 	case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
413 		return 0;
414 
415 	case PIPE_CAP_DOUBLES:
416 		if (rscreen->b.family == CHIP_ARUBA ||
417 		    rscreen->b.family == CHIP_CAYMAN ||
418 		    rscreen->b.family == CHIP_CYPRESS ||
419 		    rscreen->b.family == CHIP_HEMLOCK)
420 			return 1;
421 		return 0;
422 	case PIPE_CAP_CULL_DISTANCE:
423 		return 1;
424 
425 	case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
426 		if (family >= CHIP_CEDAR)
427 			return 256;
428 		return 0;
429 
430 	case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
431 		if (family >= CHIP_CEDAR)
432 			return 30;
433 		else
434 			return 0;
435 	/* Stream output. */
436 	case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
437 		return rscreen->b.has_streamout ? 4 : 0;
438 	case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
439 	case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
440 		return rscreen->b.has_streamout ? 1 : 0;
441 	case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
442 	case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
443 		return 32*4;
444 
445 	/* Geometry shader output. */
446 	case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
447 		return 1024;
448 	case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
449 		return 16384;
450 	case PIPE_CAP_MAX_VERTEX_STREAMS:
451 		return family >= CHIP_CEDAR ? 4 : 1;
452 
453 	case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
454 		/* Should be 2047, but 2048 is a requirement for GL 4.4 */
455 		return 2048;
456 
457 	/* Texturing. */
458 	case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
459 		if (family >= CHIP_CEDAR)
460 			return 16384;
461 		else
462 			return 8192;
463 	case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
464 		if (family >= CHIP_CEDAR)
465 			return 15;
466 		else
467 			return 14;
468 	case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
469 		/* textures support 8192, but layered rendering supports 2048 */
470 		return 12;
471 	case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
472 		/* textures support 8192, but layered rendering supports 2048 */
473 		return 2048;
474 
475 	/* Render targets. */
476 	case PIPE_CAP_MAX_RENDER_TARGETS:
477 		/* XXX some r6xx are buggy and can only do 4 */
478 		return 8;
479 
480 	case PIPE_CAP_MAX_VIEWPORTS:
481 		return R600_MAX_VIEWPORTS;
482 	case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
483 	case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
484 		return 8;
485 
486 	/* Timer queries, present when the clock frequency is non zero. */
487 	case PIPE_CAP_QUERY_TIME_ELAPSED:
488 		return rscreen->b.info.clock_crystal_freq != 0;
489 	case PIPE_CAP_QUERY_TIMESTAMP:
490 		return rscreen->b.info.drm_minor >= 20 &&
491 		       rscreen->b.info.clock_crystal_freq != 0;
492 
493 	case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
494 	case PIPE_CAP_MIN_TEXEL_OFFSET:
495 		return -8;
496 
497 	case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
498 	case PIPE_CAP_MAX_TEXEL_OFFSET:
499 		return 7;
500 
501 	case PIPE_CAP_MAX_VARYINGS:
502 		return 32;
503 
504 	case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
505 		return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
506 	case PIPE_CAP_ENDIANNESS:
507 		return PIPE_ENDIAN_LITTLE;
508 
509 	case PIPE_CAP_VENDOR_ID:
510 		return ATI_VENDOR_ID;
511 	case PIPE_CAP_DEVICE_ID:
512 		return rscreen->b.info.pci_id;
513 	case PIPE_CAP_ACCELERATED:
514 		return 1;
515 	case PIPE_CAP_VIDEO_MEMORY:
516 		return rscreen->b.info.vram_size >> 20;
517 	case PIPE_CAP_UMA:
518 		return 0;
519 	case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
520 		return rscreen->b.chip_class >= R700;
521 	case PIPE_CAP_PCI_GROUP:
522 		return rscreen->b.info.pci_domain;
523 	case PIPE_CAP_PCI_BUS:
524 		return rscreen->b.info.pci_bus;
525 	case PIPE_CAP_PCI_DEVICE:
526 		return rscreen->b.info.pci_dev;
527 	case PIPE_CAP_PCI_FUNCTION:
528 		return rscreen->b.info.pci_func;
529 
530 	case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
531 		if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
532 			return 8;
533 		return 0;
534 	case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
535 		if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
536 			return EG_MAX_ATOMIC_BUFFERS;
537 		return 0;
538 
539 	default:
540 		return u_pipe_screen_get_param_defaults(pscreen, param);
541 	}
542 }
543 
r600_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)544 static int r600_get_shader_param(struct pipe_screen* pscreen,
545 				 enum pipe_shader_type shader,
546 				 enum pipe_shader_cap param)
547 {
548 	struct r600_screen *rscreen = (struct r600_screen *)pscreen;
549 
550 	switch(shader)
551 	{
552 	case PIPE_SHADER_FRAGMENT:
553 	case PIPE_SHADER_VERTEX:
554 		break;
555 	case PIPE_SHADER_GEOMETRY:
556 		if (rscreen->b.family >= CHIP_CEDAR)
557 			break;
558 		/* pre-evergreen geom shaders need newer kernel */
559 		if (rscreen->b.info.drm_minor >= 37)
560 			break;
561 		return 0;
562 	case PIPE_SHADER_TESS_CTRL:
563 	case PIPE_SHADER_TESS_EVAL:
564 	case PIPE_SHADER_COMPUTE:
565 		if (rscreen->b.family >= CHIP_CEDAR)
566 			break;
567 		/* fallthrough */
568 	default:
569 		return 0;
570 	}
571 
572 	switch (param) {
573 	case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
574 	case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
575 	case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
576 	case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
577 		return 16384;
578 	case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
579 		return 32;
580 	case PIPE_SHADER_CAP_MAX_INPUTS:
581 		return shader == PIPE_SHADER_VERTEX ? 16 : 32;
582 	case PIPE_SHADER_CAP_MAX_OUTPUTS:
583 		return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
584 	case PIPE_SHADER_CAP_MAX_TEMPS:
585 		return 256; /* Max native temporaries. */
586 	case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
587 		if (shader == PIPE_SHADER_COMPUTE) {
588 			uint64_t max_const_buffer_size;
589 			enum pipe_shader_ir ir_type = is_nir_enabled(&rscreen->b) ?
590 				PIPE_SHADER_IR_NIR: PIPE_SHADER_IR_TGSI;
591 			pscreen->get_compute_param(pscreen, ir_type,
592 						   PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
593 						   &max_const_buffer_size);
594 			return MIN2(max_const_buffer_size, INT_MAX);
595 
596 		} else {
597 			return R600_MAX_CONST_BUFFER_SIZE;
598 		}
599 	case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
600 		return R600_MAX_USER_CONST_BUFFERS;
601 	case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
602 		return 1;
603 	case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
604 		return 1;
605 	case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
606 	case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
607 	case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
608 	case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
609 		return 1;
610 	case PIPE_SHADER_CAP_SUBROUTINES:
611 	case PIPE_SHADER_CAP_INT64_ATOMICS:
612 	case PIPE_SHADER_CAP_FP16:
613         case PIPE_SHADER_CAP_FP16_DERIVATIVES:
614         case PIPE_SHADER_CAP_INT16:
615         case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
616 		return 0;
617 	case PIPE_SHADER_CAP_INTEGERS:
618 	case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
619 		return 1;
620 	case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
621 	case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
622 		return 16;
623 	case PIPE_SHADER_CAP_PREFERRED_IR:
624 		if (is_nir_enabled(&rscreen->b))
625 			return PIPE_SHADER_IR_NIR;
626 		return PIPE_SHADER_IR_TGSI;
627 	case PIPE_SHADER_CAP_SUPPORTED_IRS: {
628 		int ir = 0;
629 		if (shader == PIPE_SHADER_COMPUTE)
630 			ir = 1 << PIPE_SHADER_IR_NATIVE;
631 		if (rscreen->b.family >= CHIP_CEDAR) {
632 			ir |= 1 << PIPE_SHADER_IR_TGSI;
633 			if (is_nir_enabled(&rscreen->b))
634 				ir |= 1 << PIPE_SHADER_IR_NIR;
635 		}
636 		return ir;
637 	}
638 	case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
639 		if (rscreen->b.family == CHIP_ARUBA ||
640 		    rscreen->b.family == CHIP_CAYMAN ||
641 		    rscreen->b.family == CHIP_CYPRESS ||
642 		    rscreen->b.family == CHIP_HEMLOCK)
643 			return 1;
644 		return 0;
645 	case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
646 	case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
647 	case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
648 	case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
649 	case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
650 		return 0;
651 	case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
652 	case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
653 		if (rscreen->b.family >= CHIP_CEDAR &&
654 		    (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE))
655 		    return 8;
656 		return 0;
657 	case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
658 		if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
659 			return 8;
660 		return 0;
661 	case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
662 		/* having to allocate the atomics out amongst shaders stages is messy,
663 		   so give compute 8 buffers and all the others one */
664 		if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics) {
665 			return EG_MAX_ATOMIC_BUFFERS;
666 		}
667 		return 0;
668 	case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
669 		/* due to a bug in the shader compiler, some loops hang
670 		 * if they are not unrolled, see:
671 		 *    https://bugs.freedesktop.org/show_bug.cgi?id=86720
672 		 */
673 		return 255;
674 	}
675 	return 0;
676 }
677 
r600_destroy_screen(struct pipe_screen * pscreen)678 static void r600_destroy_screen(struct pipe_screen* pscreen)
679 {
680 	struct r600_screen *rscreen = (struct r600_screen *)pscreen;
681 
682 	if (!rscreen)
683 		return;
684 
685 	if (!rscreen->b.ws->unref(rscreen->b.ws))
686 		return;
687 
688 	if (rscreen->global_pool) {
689 		compute_memory_pool_delete(rscreen->global_pool);
690 	}
691 
692 	r600_destroy_common_screen(&rscreen->b);
693 }
694 
r600_resource_create(struct pipe_screen * screen,const struct pipe_resource * templ)695 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
696 						  const struct pipe_resource *templ)
697 {
698 	if (templ->target == PIPE_BUFFER &&
699 	    (templ->bind & PIPE_BIND_GLOBAL))
700 		return r600_compute_global_buffer_create(screen, templ);
701 
702 	return r600_resource_create_common(screen, templ);
703 }
704 
r600_screen_create(struct radeon_winsys * ws,const struct pipe_screen_config * config)705 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws,
706 				       const struct pipe_screen_config *config)
707 {
708 	struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
709 
710 	if (!rscreen) {
711 		return NULL;
712 	}
713 
714 	/* Set functions first. */
715 	rscreen->b.b.context_create = r600_create_context;
716 	rscreen->b.b.destroy = r600_destroy_screen;
717 	rscreen->b.b.get_param = r600_get_param;
718 	rscreen->b.b.get_shader_param = r600_get_shader_param;
719 	rscreen->b.b.resource_create = r600_resource_create;
720 
721 	if (!r600_common_screen_init(&rscreen->b, ws)) {
722 		FREE(rscreen);
723 		return NULL;
724 	}
725 
726 	if (rscreen->b.info.chip_class >= EVERGREEN) {
727 		rscreen->b.b.is_format_supported = evergreen_is_format_supported;
728 	} else {
729 		rscreen->b.b.is_format_supported = r600_is_format_supported;
730 	}
731 
732 	rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
733 	if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
734 		rscreen->b.debug_flags |= DBG_COMPUTE;
735 	if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
736 		rscreen->b.debug_flags |= DBG_ALL_SHADERS | DBG_FS;
737 	if (!debug_get_bool_option("R600_HYPERZ", TRUE))
738 		rscreen->b.debug_flags |= DBG_NO_HYPERZ;
739 
740 	if (rscreen->b.family == CHIP_UNKNOWN) {
741 		fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
742 		FREE(rscreen);
743 		return NULL;
744 	}
745 
746 	/* Figure out streamout kernel support. */
747 	switch (rscreen->b.chip_class) {
748 	case R600:
749 		if (rscreen->b.family < CHIP_RS780) {
750 			rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
751 		} else {
752 			rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
753 		}
754 		break;
755 	case R700:
756 		rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
757 		break;
758 	case EVERGREEN:
759 	case CAYMAN:
760 		rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
761 		break;
762 	default:
763 		rscreen->b.has_streamout = FALSE;
764 		break;
765 	}
766 
767 	/* MSAA support. */
768 	switch (rscreen->b.chip_class) {
769 	case R600:
770 	case R700:
771 		rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
772 		rscreen->has_compressed_msaa_texturing = false;
773 		break;
774 	case EVERGREEN:
775 		rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
776 		rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
777 		break;
778 	case CAYMAN:
779 		rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
780 		rscreen->has_compressed_msaa_texturing = true;
781 		break;
782 	default:
783 		rscreen->has_msaa = FALSE;
784 		rscreen->has_compressed_msaa_texturing = false;
785 	}
786 
787 	rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
788 			      !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
789 
790 	rscreen->b.barrier_flags.cp_to_L2 =
791 		R600_CONTEXT_INV_VERTEX_CACHE |
792 		R600_CONTEXT_INV_TEX_CACHE |
793 		R600_CONTEXT_INV_CONST_CACHE;
794 	rscreen->b.barrier_flags.compute_to_L2 = R600_CONTEXT_CS_PARTIAL_FLUSH | R600_CONTEXT_FLUSH_AND_INV;
795 
796 	rscreen->global_pool = compute_memory_pool_new(rscreen);
797 
798 	/* Create the auxiliary context. This must be done last. */
799 	rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL, 0);
800 
801 	rscreen->has_atomics = rscreen->b.info.drm_minor >= 44;
802 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
803 	struct pipe_resource templ = {};
804 
805 	templ.width0 = 4;
806 	templ.height0 = 2048;
807 	templ.depth0 = 1;
808 	templ.array_size = 1;
809 	templ.target = PIPE_TEXTURE_2D;
810 	templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
811 	templ.usage = PIPE_USAGE_DEFAULT;
812 
813 	struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
814 	unsigned char *map = ws->buffer_map(res->buf, NULL, PIPE_MAP_WRITE);
815 
816 	memset(map, 0, 256);
817 
818 	r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
819 	r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
820 	r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
821 	r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
822 	r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
823 
824 	ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
825 
826 	int i;
827 	for (i = 0; i < 256; i++) {
828 		printf("%02X", map[i]);
829 		if (i % 16 == 15)
830 			printf("\n");
831 	}
832 #endif
833 
834 	if (rscreen->b.debug_flags & DBG_TEST_DMA)
835 		r600_test_dma(&rscreen->b);
836 
837 	r600_query_fix_enabled_rb_mask(&rscreen->b);
838 	return &rscreen->b.b;
839 }
840