1 /*
2 * Copyright © 2020 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <stdio.h>
25 #include <stdlib.h>
26 #include <unistd.h>
27 #include <sys/ioctl.h>
28 #include <sys/mman.h>
29 #include <sys/types.h>
30 #include <sys/socket.h>
31 #include <sys/time.h>
32 #include <sys/resource.h>
33 #include <sys/un.h>
34
35 #include "common/gen_gem.h"
36 #include "dev/gen_device_info.h"
37 #include "drm-uapi/i915_drm.h"
38 #include "drm-shim/drm_shim.h"
39 #include "util/macros.h"
40 #include "util/vma.h"
41
42 struct i915_device {
43 struct gen_device_info devinfo;
44 uint32_t device_id;
45 };
46
47 struct i915_bo {
48 struct shim_bo base;
49 };
50
51 static struct i915_device i915 = {};
52
53 bool drm_shim_driver_prefers_first_render_node = true;
54
55 static int
i915_ioctl_noop(int fd,unsigned long request,void * arg)56 i915_ioctl_noop(int fd, unsigned long request, void *arg)
57 {
58 return 0;
59 }
60
61 static int
i915_ioctl_gem_create(int fd,unsigned long request,void * arg)62 i915_ioctl_gem_create(int fd, unsigned long request, void *arg)
63 {
64 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
65 struct drm_i915_gem_create *create = arg;
66 struct i915_bo *bo = calloc(1, sizeof(*bo));
67
68 drm_shim_bo_init(&bo->base, create->size);
69
70 create->handle = drm_shim_bo_get_handle(shim_fd, &bo->base);
71
72 drm_shim_bo_put(&bo->base);
73
74 return 0;
75 }
76
77 static int
i915_ioctl_gem_mmap(int fd,unsigned long request,void * arg)78 i915_ioctl_gem_mmap(int fd, unsigned long request, void *arg)
79 {
80 struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
81 struct drm_i915_gem_mmap *mmap_arg = arg;
82 struct shim_bo *bo = drm_shim_bo_lookup(shim_fd, mmap_arg->handle);
83
84 if (!bo)
85 return -1;
86
87 if (!bo->map)
88 bo->map = drm_shim_mmap(shim_fd, bo->size, PROT_READ | PROT_WRITE, MAP_SHARED, -1, (uintptr_t)bo);
89
90 mmap_arg->addr_ptr = (uint64_t) (bo->map + mmap_arg->offset);
91
92 return 0;
93 }
94
95 static int
i915_ioctl_gem_context_create(int fd,unsigned long request,void * arg)96 i915_ioctl_gem_context_create(int fd, unsigned long request, void *arg)
97 {
98 struct drm_i915_gem_context_create *create = arg;
99
100 create->ctx_id = 1; /* Just return a fake non zero ID. */
101
102 return 0;
103 }
104
105 static int
i915_ioctl_gem_context_getparam(int fd,unsigned long request,void * arg)106 i915_ioctl_gem_context_getparam(int fd, unsigned long request, void *arg)
107 {
108 struct drm_i915_gem_context_param *param = arg;
109
110 if (param->param == I915_CONTEXT_PARAM_GTT_SIZE) {
111 if (i915.devinfo.gen >= 8 && !i915.devinfo.is_cherryview)
112 param->value = 1ull << 48;
113 else
114 param->value = 1ull << 31;
115 } else {
116 param->value = 0;
117 }
118
119 return 0;
120 }
121
122 static int
i915_ioctl_get_param(int fd,unsigned long request,void * arg)123 i915_ioctl_get_param(int fd, unsigned long request, void *arg)
124 {
125 drm_i915_getparam_t *gp = arg;
126
127 switch (gp->param) {
128 case I915_PARAM_CHIPSET_ID:
129 *gp->value = i915.device_id;
130 return 0;
131 case I915_PARAM_REVISION:
132 *gp->value = 0;
133 return 0;
134 case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
135 *gp->value = i915.devinfo.timestamp_frequency;
136 return 0;
137 case I915_PARAM_HAS_ALIASING_PPGTT:
138 if (i915.devinfo.gen < 6)
139 *gp->value = I915_GEM_PPGTT_NONE;
140 else if (i915.devinfo.gen <= 7)
141 *gp->value = I915_GEM_PPGTT_ALIASING;
142 else
143 *gp->value = I915_GEM_PPGTT_FULL;
144 return 0;
145
146 case I915_PARAM_NUM_FENCES_AVAIL:
147 *gp->value = 8; /* gen2/3 value, unused in brw/iris */
148 return 0;
149
150 case I915_PARAM_HAS_BLT:
151 *gp->value = 1; /* gen2/3 value, unused in brw/iris */
152 return 0;
153
154 case I915_PARAM_HAS_BSD:
155 case I915_PARAM_HAS_LLC:
156 case I915_PARAM_HAS_VEBOX:
157 *gp->value = 0; /* gen2/3 value, unused in brw/iris */
158 return 0;
159
160 case I915_PARAM_HAS_GEM:
161 case I915_PARAM_HAS_RELAXED_DELTA:
162 case I915_PARAM_HAS_RELAXED_FENCING:
163 case I915_PARAM_HAS_WAIT_TIMEOUT:
164 case I915_PARAM_HAS_EXECBUF2:
165 case I915_PARAM_HAS_EXEC_SOFTPIN:
166 case I915_PARAM_HAS_EXEC_CAPTURE:
167 case I915_PARAM_HAS_EXEC_FENCE:
168 case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
169 case I915_PARAM_HAS_CONTEXT_ISOLATION:
170 case I915_PARAM_HAS_EXEC_ASYNC:
171 case I915_PARAM_HAS_EXEC_NO_RELOC:
172 case I915_PARAM_HAS_EXEC_BATCH_FIRST:
173 *gp->value = true;
174 return 0;
175 case I915_PARAM_CMD_PARSER_VERSION:
176 /* Most recent version in drivers/gpu/drm/i915/i915_cmd_parser.c */
177 *gp->value = 10;
178 return 0;
179 case I915_PARAM_MMAP_VERSION:
180 case I915_PARAM_MMAP_GTT_VERSION:
181 *gp->value = 1;
182 return 0;
183 case I915_PARAM_SUBSLICE_TOTAL:
184 *gp->value = 0;
185 for (uint32_t s = 0; s < i915.devinfo.num_slices; s++)
186 *gp->value += i915.devinfo.num_subslices[s];
187 return 0;
188 case I915_PARAM_EU_TOTAL:
189 *gp->value = 0;
190 for (uint32_t s = 0; s < i915.devinfo.num_slices; s++)
191 *gp->value += i915.devinfo.num_subslices[s] * i915.devinfo.num_eu_per_subslice;
192 return 0;
193 case I915_PARAM_PERF_REVISION:
194 *gp->value = 3;
195 return 0;
196 default:
197 break;
198 }
199
200 fprintf(stderr, "Unknown DRM_IOCTL_I915_GET_PARAM %d\n", gp->param);
201 return -1;
202 }
203
204 static int
query_write_topology(struct drm_i915_query_item * item)205 query_write_topology(struct drm_i915_query_item *item)
206 {
207 struct drm_i915_query_topology_info *info =
208 (void *) (uintptr_t) item->data_ptr;
209 int32_t length =
210 sizeof(*info) +
211 DIV_ROUND_UP(i915.devinfo.num_slices, 8) +
212 i915.devinfo.num_slices * DIV_ROUND_UP(i915.devinfo.num_subslices[0], 8) +
213 i915.devinfo.num_slices * i915.devinfo.num_subslices[0] *
214 DIV_ROUND_UP(i915.devinfo.num_eu_per_subslice, 8);
215
216 if (item->length == 0) {
217 item->length = length;
218 return 0;
219 }
220
221 if (item->length < length) {
222 fprintf(stderr, "size too small\n");
223 return -EINVAL;
224 }
225
226 if (info->flags) {
227 fprintf(stderr, "invalid topology flags\n");
228 return -EINVAL;
229 }
230
231 info->max_slices = i915.devinfo.num_slices;
232 info->max_subslices = i915.devinfo.num_subslices[0];
233 info->max_eus_per_subslice = i915.devinfo.num_eu_per_subslice;
234
235 info->subslice_offset = DIV_ROUND_UP(i915.devinfo.num_slices, 8);
236 info->subslice_stride = DIV_ROUND_UP(i915.devinfo.num_subslices[0], 8);
237 info->eu_offset = info->subslice_offset + info->max_slices * info->subslice_stride;
238
239 uint32_t slice_mask = (1u << i915.devinfo.num_slices) - 1;
240 for (uint32_t i = 0; i < info->subslice_offset; i++)
241 info->data[i] = (slice_mask >> (8 * i)) & 0xff;
242
243 for (uint32_t s = 0; s < i915.devinfo.num_slices; s++) {
244 uint32_t subslice_mask = (1u << i915.devinfo.num_subslices[s]) - 1;
245 for (uint32_t i = 0; i < info->subslice_stride; i++) {
246 info->data[info->subslice_offset + s * info->subslice_stride + i] =
247 (subslice_mask >> (8 * i)) & 0xff;
248 }
249 }
250
251 for (uint32_t s = 0; s < i915.devinfo.num_slices; s++) {
252 for (uint32_t ss = 0; ss < i915.devinfo.num_subslices[s]; ss++) {
253 uint32_t eu_mask = (1u << info->max_eus_per_subslice) - 1;
254 for (uint32_t i = 0; i < DIV_ROUND_UP(info->max_eus_per_subslice, 8); i++) {
255 info->data[info->eu_offset +
256 (s * info->max_subslices + ss) * DIV_ROUND_UP(info->max_eus_per_subslice, 8) + i] =
257 (eu_mask >> (8 * i)) & 0xff;
258 }
259 }
260 }
261
262 return 0;
263 }
264
265 static int
i915_ioctl_query(int fd,unsigned long request,void * arg)266 i915_ioctl_query(int fd, unsigned long request, void *arg)
267 {
268 struct drm_i915_query *query = arg;
269 struct drm_i915_query_item *items = (void *) (uintptr_t) query->items_ptr;
270
271 if (query->flags) {
272 fprintf(stderr, "invalid query flags\n");
273 return -EINVAL;
274 }
275
276 for (uint32_t i = 0; i < query->num_items; i++) {
277 struct drm_i915_query_item *item = &items[i];
278
279 switch (item->query_id) {
280 case DRM_I915_QUERY_TOPOLOGY_INFO: {
281 int ret = query_write_topology(item);
282 if (ret)
283 item->length = ret;
284 break;
285 }
286
287 default:
288 fprintf(stderr, "Unknown drm_i915_query_item id=%lli\n", item->query_id);
289 item->length = -EINVAL;
290 break;
291 }
292 }
293
294 return 0;
295 }
296
297 static int
i915_gem_get_aperture(int fd,unsigned long request,void * arg)298 i915_gem_get_aperture(int fd, unsigned long request, void *arg)
299 {
300 struct drm_i915_gem_get_aperture *aperture = arg;
301
302 if (i915.devinfo.gen >= 8 &&
303 !i915.devinfo.is_cherryview) {
304 aperture->aper_size = 1ull << 48;
305 aperture->aper_available_size = 1ull << 48;
306 } else {
307 aperture->aper_size = 1ull << 31;
308 aperture->aper_size = 1ull << 31;
309 }
310
311 return 0;
312 }
313
314 static ioctl_fn_t driver_ioctls[] = {
315 [DRM_I915_GETPARAM] = i915_ioctl_get_param,
316 [DRM_I915_QUERY] = i915_ioctl_query,
317
318 [DRM_I915_GET_RESET_STATS] = i915_ioctl_noop,
319
320 [DRM_I915_GEM_CREATE] = i915_ioctl_gem_create,
321 [DRM_I915_GEM_MMAP] = i915_ioctl_gem_mmap,
322 [DRM_I915_GEM_SET_TILING] = i915_ioctl_noop,
323 [DRM_I915_GEM_CONTEXT_CREATE] = i915_ioctl_gem_context_create,
324 [DRM_I915_GEM_CONTEXT_DESTROY] = i915_ioctl_noop,
325 [DRM_I915_GEM_CONTEXT_GETPARAM] = i915_ioctl_gem_context_getparam,
326 [DRM_I915_GEM_CONTEXT_SETPARAM] = i915_ioctl_noop,
327 [DRM_I915_GEM_EXECBUFFER2] = i915_ioctl_noop,
328 [DRM_I915_GEM_EXECBUFFER2_WR] = i915_ioctl_noop,
329
330 [DRM_I915_GEM_GET_APERTURE] = i915_gem_get_aperture,
331
332 [DRM_I915_REG_READ] = i915_ioctl_noop,
333
334 [DRM_I915_GEM_SET_DOMAIN] = i915_ioctl_noop,
335 [DRM_I915_GEM_GET_CACHING] = i915_ioctl_noop,
336 [DRM_I915_GEM_SET_CACHING] = i915_ioctl_noop,
337 [DRM_I915_GEM_MADVISE] = i915_ioctl_noop,
338 [DRM_I915_GEM_WAIT] = i915_ioctl_noop,
339 [DRM_I915_GEM_BUSY] = i915_ioctl_noop,
340 };
341
342 void
drm_shim_driver_init(void)343 drm_shim_driver_init(void)
344 {
345 const char *user_platform = getenv("INTEL_STUB_GPU_PLATFORM");
346
347 /* Use SKL if nothing is specified. */
348 i915.device_id = gen_device_name_to_pci_device_id(user_platform ?: "skl");
349 if (!gen_get_device_info_from_pci_id(i915.device_id, &i915.devinfo))
350 return;
351
352 shim_device.bus_type = DRM_BUS_PCI;
353 shim_device.driver_name = "i915";
354 shim_device.driver_ioctls = driver_ioctls;
355 shim_device.driver_ioctl_count = ARRAY_SIZE(driver_ioctls);
356
357 char uevent_content[1024];
358 snprintf(uevent_content, sizeof(uevent_content),
359 "DRIVER=i915\n"
360 "PCI_CLASS=30000\n"
361 "PCI_ID=8086:%x\n"
362 "PCI_SUBSYS_ID=1028:075B\n"
363 "PCI_SLOT_NAME=0000:00:02.0\n"
364 "MODALIAS=pci:v00008086d00005916sv00001028sd0000075Bbc03sc00i00\n",
365 i915.device_id);
366 drm_shim_override_file(uevent_content,
367 "/sys/dev/char/%d:%d/device/uevent",
368 DRM_MAJOR, render_node_minor);
369 drm_shim_override_file("0x0\n",
370 "/sys/dev/char/%d:%d/device/revision",
371 DRM_MAJOR, render_node_minor);
372 char device_content[10];
373 snprintf(device_content, sizeof(device_content),
374 "0x%x\n", i915.device_id);
375 drm_shim_override_file("0x8086",
376 "/sys/dev/char/%d:%d/device/vendor",
377 DRM_MAJOR, render_node_minor);
378 drm_shim_override_file("0x8086",
379 "/sys/devices/pci0000:00/0000:00:02.0/vendor");
380 drm_shim_override_file(device_content,
381 "/sys/dev/char/%d:%d/device/device",
382 DRM_MAJOR, render_node_minor);
383 drm_shim_override_file(device_content,
384 "/sys/devices/pci0000:00/0000:00:02.0/device");
385 drm_shim_override_file("0x1234",
386 "/sys/dev/char/%d:%d/device/subsystem_vendor",
387 DRM_MAJOR, render_node_minor);
388 drm_shim_override_file("0x1234",
389 "/sys/devices/pci0000:00/0000:00:02.0/subsystem_vendor");
390 drm_shim_override_file("0x1234",
391 "/sys/dev/char/%d:%d/device/subsystem_device",
392 DRM_MAJOR, render_node_minor);
393 drm_shim_override_file("0x1234",
394 "/sys/devices/pci0000:00/0000:00:02.0/subsystem_device");
395 }
396